URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_rom.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5477d 17h	/8051/trunk/rtl/verilog/oc8051_rom.v
185		root	5533d 18h	/8051/trunk/rtl/verilog/oc8051_rom.v
179	add /* synopsys xx_case */ to case statments.	simont	7612d 11h	/8051/trunk/rtl/verilog/oc8051_rom.v
149	pipelined acces to axternal instruction interface added.	simont	7640d 15h	/8051/trunk/rtl/verilog/oc8051_rom.v
109	add `include "oc8051_defines.v"	simont	7701d 13h	/8051/trunk/rtl/verilog/oc8051_rom.v
92	initial inport	simont	7702d 21h	/8051/trunk/rtl/verilog/oc8051_rom.v