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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Rev 186

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Rev Log message Author Age Path
186 root 5477d 18h /8051/trunk/rtl/verilog/oc8051_top.v
185 root 5533d 20h /8051/trunk/rtl/verilog/oc8051_top.v
181 Simulation reports added. simont 7612d 12h /8051/trunk/rtl/verilog/oc8051_top.v
174 ram modules added. simont 7623d 20h /8051/trunk/rtl/verilog/oc8051_top.v
172 BIST signals added. simont 7626d 19h /8051/trunk/rtl/verilog/oc8051_top.v
148 include "8051_defines" added. simont 7640d 17h /8051/trunk/rtl/verilog/oc8051_top.v
144 chsnge comp.des to des1 simont 7667d 21h /8051/trunk/rtl/verilog/oc8051_top.v
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7669d 00h /8051/trunk/rtl/verilog/oc8051_top.v
139 add aditional alu destination to solve critical path. simont 7669d 18h /8051/trunk/rtl/verilog/oc8051_top.v
134 fix bug in case execution of two data dependent instructions. simont 7675d 22h /8051/trunk/rtl/verilog/oc8051_top.v
132 change branch instruction execution (reduse needed clock periods). simont 7679d 16h /8051/trunk/rtl/verilog/oc8051_top.v
122 deifne OC8051_ROM added simont 7693d 23h /8051/trunk/rtl/verilog/oc8051_top.v
120 defines for pherypherals added simont 7694d 21h /8051/trunk/rtl/verilog/oc8051_top.v
118 change wr_sft to 2 bit wire. simont 7695d 17h /8051/trunk/rtl/verilog/oc8051_top.v
117 Register oc8051_sfr dato output, add signal wait_data. simont 7695d 18h /8051/trunk/rtl/verilog/oc8051_top.v
107 Include instruction cache. simont 7701d 14h /8051/trunk/rtl/verilog/oc8051_top.v
102 raname signals. simont 7702d 18h /8051/trunk/rtl/verilog/oc8051_top.v
82 replace some modules simont 7781d 19h /8051/trunk/rtl/verilog/oc8051_top.v
76 add module oc8051_sfr, 256 bytes internal ram simont 7850d 16h /8051/trunk/rtl/verilog/oc8051_top.v
72 fix bug in interface to external data ram simont 7858d 19h /8051/trunk/rtl/verilog/oc8051_top.v

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