URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Rev 186

Rev	Log message	Author	Age	Path
62	fix bugs in instruction interface	simont	7877d 14h	/8051/trunk/rtl/verilog/oc8051_top.v
54	cahnge interface to instruction rom	simont	7883d 12h	/8051/trunk/rtl/verilog/oc8051_top.v
46	prepared header	simont	7900d 14h	/8051/trunk/rtl/verilog/oc8051_top.v
37	added signals ack, stb and cyc	simont	7927d 16h	/8051/trunk/rtl/verilog/oc8051_top.v
28	remove syn signal	simont	7938d 20h	/8051/trunk/rtl/verilog/oc8051_top.v
26	main divider logic was optimized not optimized by compiler, so I did it by hand	markom	7938d 22h	/8051/trunk/rtl/verilog/oc8051_top.v
19	combinatorial loop removed	simont	7941d 12h	/8051/trunk/rtl/verilog/oc8051_top.v
17	fix some bugs	simont	7944d 17h	/8051/trunk/rtl/verilog/oc8051_top.v
12	des1_r in alu port list	simont	7945d 16h	/8051/trunk/rtl/verilog/oc8051_top.v
9	removed unused compare states	markom	7947d 14h	/8051/trunk/rtl/verilog/oc8051_top.v