OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [sim/] - Rev 186

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Rev Log message Author Age Path
186 root 5495d 17h /8051/trunk/sim/
185 root 5551d 18h /8051/trunk/sim/
176 ram modules added. simont 7641d 18h /8051/trunk/sim/
168 modify program list. simont 7652d 16h /8051/trunk/sim/
162 initial inport. simont 7656d 20h /8051/trunk/sim/
161 fix file names. simont 7656d 20h /8051/trunk/sim/
159 initial inport. simont 7656d 20h /8051/trunk/sim/
154 File name fixed. simont 7657d 15h /8051/trunk/sim/
106 generic_dpram used simont 7720d 16h /8051/trunk/sim/
101 initial inport simont 7720d 20h /8051/trunk/sim/
100 use \ simont 7720d 20h /8051/trunk/sim/
99 change directory structure simont 7720d 20h /8051/trunk/sim/
98 move to rtl/verilog simont 7720d 20h /8051/trunk/sim/
85 prepare bugs simont 7791d 18h /8051/trunk/sim/
83 replace some modules simont 7799d 17h /8051/trunk/sim/
82 replace some modules simont 7799d 18h /8051/trunk/sim/
69 add parameters simont 7880d 18h /8051/trunk/sim/
66 added xrom_test simont 7881d 15h /8051/trunk/sim/
65 add oc8051_icache and oc8051_cache_ram simont 7881d 15h /8051/trunk/sim/
64 signal es_int=1'b0 simont 7881d 15h /8051/trunk/sim/
63 initial import simont 7881d 15h /8051/trunk/sim/
58 add external rom testing simont 7887d 13h /8051/trunk/sim/
57 add module oc8051_xrom simont 7887d 13h /8051/trunk/sim/
56 initial CVS input simont 7887d 13h /8051/trunk/sim/
55 added parameter DELAY simont 7887d 13h /8051/trunk/sim/
46 prepared header simont 7904d 14h /8051/trunk/sim/
43 remove unused files simont 7904d 16h /8051/trunk/sim/
42 *** empty log message *** simont 7904d 16h /8051/trunk/sim/
41 remove unused files simont 7904d 16h /8051/trunk/sim/
37 added signals ack, stb and cyc simont 7931d 17h /8051/trunk/sim/

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