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21 Fix overrun and underrun interrupts bug

The overrun and underrun did not have any logic for
resetting their signals, this patch changes that so
that the interrupt signal is only on when the event
happens. The interrupt will be latched into
the interrupt status register anyway, so keeping it
high for (in worst case) one clock cycle is enough.
stekern 4674d 09h /
20 root 5471d 21h /
19 root 5527d 22h /
18 Added old uploaded documents to new repository. root 5528d 01h /
17 New directory structure. root 5528d 01h /
16 Fixed a bug in the IN-FIFO - 18 bit samples where not alligned correctly. rudi 7835d 19h /
15 Updated copyright header. rudi 7892d 06h /
14 Fixed a bug reported by Igor. Apparently this bug only shows up when
the WB clock is very low (2x bit_clk). Updated Copyright header.
rudi 7892d 06h /
13 Changed the datasheet and STATUS.txt rudi 7892d 06h /
12 - Added defines to select fifo depth between 4, 8 and 16 entries. rudi 8084d 09h /
11 - fixed spelling rudi 8090d 07h /
10 - Fixed the order of the thrash hold bits to match the spec.
- Many minor synthesis cleanup items ...
rudi 8090d 07h /
9 *** empty log message *** rudi 8110d 03h /
8 Simulation Makefile rudi 8110d 03h /
7 Added test bench for public release rudi 8110d 04h /
6 - Removed RTY_O output.
- Added Clock and Reset Inputs to documentation.
- Changed IO names to be more clear.
- Uniquifyed define names to be core specific.
rudi 8297d 04h /
5 Added Directory Tree Description to README file rudi 8300d 04h /
4 - Changed to new directory structure rudi 8304d 05h /
3 This commit was manufactured by cvs2svn to create tag 'start'. 8380d 10h /
2 Initial Checkin rudi 8380d 10h /

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