URL https://opencores.org/ocsvn/ae18/ae18/trunk

Subversion Repositories ae18

[/] [ae18/] [trunk/] [rtl/] [verilog/] - Rev 20

Rev	Log message	Author	Age	Path
20	New directory structure.	root	5551d 00h	/ae18/trunk/rtl/verilog/
18	Fixed CPFSLT/CPFSGT bug discovered by G. M. Gallant.	sybreon	6066d 00h	/ae18/trunk/rtl/verilog/
17	Moved testbench into sim/verilog/testbench.v Minor cleanup.	sybreon	6246d 20h	/ae18/trunk/rtl/verilog/
15	Fixed various bugs: - STATUS,C not correct for subtraction instructions - Data memory indirect addressing mode bugs - Other minor fixes	sybreon	6256d 20h	/ae18/trunk/rtl/verilog/
14	Minor simulation changes.	sybreon	6256d 20h	/ae18/trunk/rtl/verilog/
12	Rearranged code to make it synthesisable.	sybreon	6286d 19h	/ae18/trunk/rtl/verilog/
10	Minor code clean up	sybreon	6352d 00h	/ae18/trunk/rtl/verilog/
9	Minor clean up	sybreon	6352d 00h	/ae18/trunk/rtl/verilog/
8	* empty log message *	sybreon	6352d 00h	/ae18/trunk/rtl/verilog/
7	added $Log$	sybreon	6352d 00h	/ae18/trunk/rtl/verilog/
6	* empty log message *	sybreon	6352d 00h	/ae18/trunk/rtl/verilog/
4	Minor bug fix for PCL read/write	sybreon	6352d 01h	/ae18/trunk/rtl/verilog/
3	Minor bug fix.	sybreon	6352d 10h	/ae18/trunk/rtl/verilog/
2	initial checkin	sybreon	6353d 03h	/ae18/trunk/rtl/verilog/