URL https://opencores.org/ocsvn/aes_highthroughput_lowarea/aes_highthroughput_lowarea/trunk

Subversion Repositories aes_highthroughput_lowarea

[/] - Rev 8

Rev	Log message	Author	Age	Path
8	Added core specification document, core top example module and FPGA synthesis project files.	motilito	4432d 13h	/
7	Added AES KAT test bench and simulation batch files for Icarus Verilog. Note that reset polarity was changed to rising edge (posedge).	motilito	4887d 11h	/
6	Correcting some problems with bench directory	motilito	4887d 15h	/
5	Updating sub-directory structure	motilito	4887d 15h	/
4	Moving RTL to verilog sub-directory	motilito	4887d 15h	/
3	Building new directory structure.	motilito	4888d 01h	/
2	initial release	rainrhythm	5189d 07h	/
1	The project and the structure was created	root	5191d 17h	/