URL https://opencores.org/ocsvn/aes_highthroughput_lowarea/aes_highthroughput_lowarea/trunk

Subversion Repositories aes_highthroughput_lowarea

[/] [aes_highthroughput_lowarea/] [trunk/] - Rev 9

Rev	Log message	Author	Age	Path
9	Corrected block diagram with the size of i_key_mode input signal.	motilito	4431d 12h	/aes_highthroughput_lowarea/trunk/
8	Added core specification document, core top example module and FPGA synthesis project files.	motilito	4431d 23h	/aes_highthroughput_lowarea/trunk/
7	Added AES KAT test bench and simulation batch files for Icarus Verilog. Note that reset polarity was changed to rising edge (posedge).	motilito	4886d 21h	/aes_highthroughput_lowarea/trunk/
6	Correcting some problems with bench directory	motilito	4887d 02h	/aes_highthroughput_lowarea/trunk/
5	Updating sub-directory structure	motilito	4887d 02h	/aes_highthroughput_lowarea/trunk/
4	Moving RTL to verilog sub-directory	motilito	4887d 02h	/aes_highthroughput_lowarea/trunk/
3	Building new directory structure.	motilito	4887d 12h	/aes_highthroughput_lowarea/trunk/
2	initial release	rainrhythm	5188d 18h	/aes_highthroughput_lowarea/trunk/
1	The project and the structure was created	root	5191d 04h	/aes_highthroughput_lowarea/trunk/