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31 Added initial Xilinx Vivado synthesis scripts and constraints. daniel.kho 3772d 18h /
30 Refactored synthesis scripts. daniel.kho 3772d 19h /
29 Updated simulation scripts. daniel.kho 3772d 19h /
28 Temporarily remove simulation folder. daniel.kho 3772d 19h /
27 Updated simulation scripts. daniel.kho 3772d 19h /
26 Refactored simulation folders. daniel.kho 3772d 19h /
25 Refactored folders. daniel.kho 3772d 20h /
24 Updated simulation sources to reflect changes made for synthesis. daniel.kho 3772d 20h /
23 Added top-level user example used in technical paper. daniel.kho 3780d 14h /
22 Added pin assignments for BeMicro kit. Added demo top-level used in technical paper. daniel.kho 3780d 14h /
21 Added synthesis files for Vivado. The RTL have not yet been updated with the latest changes available in the Quartus version. daniel.kho 3783d 16h /
20 Updated simulation scripts. daniel.kho 3783d 16h /
19 Updated synthesis constraints and scripts. daniel.kho 3783d 16h /
18 Added hardware PRBS generator, modularised top-level by having separate file as the tester. daniel.kho 3783d 16h /
17 Added more pipelining, enhancements. Tested on BeMicro kit. daniel.kho 3783d 16h /
16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 3886d 13h /
15 [minor]: cleaned up sources. daniel.kho 3888d 19h /
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 3897d 10h /
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 3897d 14h /
12 Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. daniel.kho 3906d 18h /

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