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26 Refactored simulation folders. daniel.kho 3761d 16h /axi4_tlm_bfm/
25 Refactored folders. daniel.kho 3761d 17h /axi4_tlm_bfm/
24 Updated simulation sources to reflect changes made for synthesis. daniel.kho 3761d 17h /axi4_tlm_bfm/
23 Added top-level user example used in technical paper. daniel.kho 3769d 11h /axi4_tlm_bfm/
22 Added pin assignments for BeMicro kit. Added demo top-level used in technical paper. daniel.kho 3769d 11h /axi4_tlm_bfm/
21 Added synthesis files for Vivado. The RTL have not yet been updated with the latest changes available in the Quartus version. daniel.kho 3772d 13h /axi4_tlm_bfm/
20 Updated simulation scripts. daniel.kho 3772d 13h /axi4_tlm_bfm/
19 Updated synthesis constraints and scripts. daniel.kho 3772d 13h /axi4_tlm_bfm/
18 Added hardware PRBS generator, modularised top-level by having separate file as the tester. daniel.kho 3772d 13h /axi4_tlm_bfm/
17 Added more pipelining, enhancements. Tested on BeMicro kit. daniel.kho 3772d 14h /axi4_tlm_bfm/
16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 3875d 10h /axi4_tlm_bfm/
15 [minor]: cleaned up sources. daniel.kho 3877d 16h /axi4_tlm_bfm/
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 3886d 07h /axi4_tlm_bfm/
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 3886d 11h /axi4_tlm_bfm/
12 Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. daniel.kho 3895d 16h /axi4_tlm_bfm/
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 3897d 10h /axi4_tlm_bfm/
10 Written a few more directed testcases (in user.vhdl), and fixed several bugs. TODO move the testcases to the stimuli folder. daniel.kho 3901d 10h /axi4_tlm_bfm/
9 Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. daniel.kho 3904d 06h /axi4_tlm_bfm/
8 [minor]: removed writeStream(). The write() procedure can be used for both stream and non-stream interfaces. For stream interfaces, just map the address argument to don't-cares. Made several other minor enhancements, simplifications. daniel.kho 4004d 12h /axi4_tlm_bfm/
7 [minor]: renamed axi4-stream-bfm.vhdl to axi4-stream-bfm-master.vhdl so as to allow a future implementation of the AXI4-Stream slave / receiver. Changed simulation script to start GUI simulation only when there are no errors (previously, it brings up the GUI even when there are compilation errors). daniel.kho 4008d 06h /axi4_tlm_bfm/

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