OpenCores
URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

[/] [axi4_tlm_bfm/] - Rev 28

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
28 Temporarily remove simulation folder. daniel.kho 3762d 00h /axi4_tlm_bfm/
27 Updated simulation scripts. daniel.kho 3762d 00h /axi4_tlm_bfm/
26 Refactored simulation folders. daniel.kho 3762d 01h /axi4_tlm_bfm/
25 Refactored folders. daniel.kho 3762d 01h /axi4_tlm_bfm/
24 Updated simulation sources to reflect changes made for synthesis. daniel.kho 3762d 02h /axi4_tlm_bfm/
23 Added top-level user example used in technical paper. daniel.kho 3769d 19h /axi4_tlm_bfm/
22 Added pin assignments for BeMicro kit. Added demo top-level used in technical paper. daniel.kho 3769d 19h /axi4_tlm_bfm/
21 Added synthesis files for Vivado. The RTL have not yet been updated with the latest changes available in the Quartus version. daniel.kho 3772d 22h /axi4_tlm_bfm/
20 Updated simulation scripts. daniel.kho 3772d 22h /axi4_tlm_bfm/
19 Updated synthesis constraints and scripts. daniel.kho 3772d 22h /axi4_tlm_bfm/
18 Added hardware PRBS generator, modularised top-level by having separate file as the tester. daniel.kho 3772d 22h /axi4_tlm_bfm/
17 Added more pipelining, enhancements. Tested on BeMicro kit. daniel.kho 3772d 22h /axi4_tlm_bfm/
16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 3875d 18h /axi4_tlm_bfm/
15 [minor]: cleaned up sources. daniel.kho 3878d 01h /axi4_tlm_bfm/
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 3886d 15h /axi4_tlm_bfm/
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 3886d 20h /axi4_tlm_bfm/
12 Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. daniel.kho 3896d 00h /axi4_tlm_bfm/
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 3897d 18h /axi4_tlm_bfm/
10 Written a few more directed testcases (in user.vhdl), and fixed several bugs. TODO move the testcases to the stimuli folder. daniel.kho 3901d 19h /axi4_tlm_bfm/
9 Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. daniel.kho 3904d 15h /axi4_tlm_bfm/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.