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[/] [axi4_tlm_bfm/] - Rev 32

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32 Added compile+simulate script for Windows. daniel.kho 3747d 23h /axi4_tlm_bfm/
31 Added initial Xilinx Vivado synthesis scripts and constraints. daniel.kho 3761d 21h /axi4_tlm_bfm/
30 Refactored synthesis scripts. daniel.kho 3761d 21h /axi4_tlm_bfm/
29 Updated simulation scripts. daniel.kho 3761d 22h /axi4_tlm_bfm/
28 Temporarily remove simulation folder. daniel.kho 3761d 22h /axi4_tlm_bfm/
27 Updated simulation scripts. daniel.kho 3761d 22h /axi4_tlm_bfm/
26 Refactored simulation folders. daniel.kho 3761d 22h /axi4_tlm_bfm/
25 Refactored folders. daniel.kho 3761d 23h /axi4_tlm_bfm/
24 Updated simulation sources to reflect changes made for synthesis. daniel.kho 3761d 23h /axi4_tlm_bfm/
23 Added top-level user example used in technical paper. daniel.kho 3769d 17h /axi4_tlm_bfm/
22 Added pin assignments for BeMicro kit. Added demo top-level used in technical paper. daniel.kho 3769d 17h /axi4_tlm_bfm/
21 Added synthesis files for Vivado. The RTL have not yet been updated with the latest changes available in the Quartus version. daniel.kho 3772d 19h /axi4_tlm_bfm/
20 Updated simulation scripts. daniel.kho 3772d 19h /axi4_tlm_bfm/
19 Updated synthesis constraints and scripts. daniel.kho 3772d 19h /axi4_tlm_bfm/
18 Added hardware PRBS generator, modularised top-level by having separate file as the tester. daniel.kho 3772d 19h /axi4_tlm_bfm/
17 Added more pipelining, enhancements. Tested on BeMicro kit. daniel.kho 3772d 19h /axi4_tlm_bfm/
16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 3875d 16h /axi4_tlm_bfm/
15 [minor]: cleaned up sources. daniel.kho 3877d 22h /axi4_tlm_bfm/
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 3886d 12h /axi4_tlm_bfm/
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 3886d 17h /axi4_tlm_bfm/

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