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[/] [axi4_tlm_bfm/] [trunk/] - Rev 29

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29 Updated simulation scripts. daniel.kho 3774d 22h /axi4_tlm_bfm/trunk/
28 Temporarily remove simulation folder. daniel.kho 3774d 22h /axi4_tlm_bfm/trunk/
27 Updated simulation scripts. daniel.kho 3774d 22h /axi4_tlm_bfm/trunk/
26 Refactored simulation folders. daniel.kho 3774d 22h /axi4_tlm_bfm/trunk/
25 Refactored folders. daniel.kho 3774d 23h /axi4_tlm_bfm/trunk/
24 Updated simulation sources to reflect changes made for synthesis. daniel.kho 3774d 23h /axi4_tlm_bfm/trunk/
23 Added top-level user example used in technical paper. daniel.kho 3782d 17h /axi4_tlm_bfm/trunk/
22 Added pin assignments for BeMicro kit. Added demo top-level used in technical paper. daniel.kho 3782d 17h /axi4_tlm_bfm/trunk/
21 Added synthesis files for Vivado. The RTL have not yet been updated with the latest changes available in the Quartus version. daniel.kho 3785d 19h /axi4_tlm_bfm/trunk/
20 Updated simulation scripts. daniel.kho 3785d 19h /axi4_tlm_bfm/trunk/
19 Updated synthesis constraints and scripts. daniel.kho 3785d 19h /axi4_tlm_bfm/trunk/
18 Added hardware PRBS generator, modularised top-level by having separate file as the tester. daniel.kho 3785d 19h /axi4_tlm_bfm/trunk/
17 Added more pipelining, enhancements. Tested on BeMicro kit. daniel.kho 3785d 19h /axi4_tlm_bfm/trunk/
16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 3888d 16h /axi4_tlm_bfm/trunk/
15 [minor]: cleaned up sources. daniel.kho 3890d 22h /axi4_tlm_bfm/trunk/
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 3899d 13h /axi4_tlm_bfm/trunk/
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 3899d 17h /axi4_tlm_bfm/trunk/
12 Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. daniel.kho 3908d 21h /axi4_tlm_bfm/trunk/
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 3910d 16h /axi4_tlm_bfm/trunk/
10 Written a few more directed testcases (in user.vhdl), and fixed several bugs. TODO move the testcases to the stimuli folder. daniel.kho 3914d 16h /axi4_tlm_bfm/trunk/

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