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[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [quartus-synthesis/] [user.vhdl] - Rev 44

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44 Committed latest changes to Quartus synthesis folder and some minor changes. daniel.kho 3329d 05h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/user.vhdl
42 Major enhancements and bugfix. Used DDR for AXI BFM for enhanced functionality and performance. Tested in simulation; TODO update synthesis design files. daniel.kho 3674d 05h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/user.vhdl
17 Added more pipelining, enhancements. Tested on BeMicro kit. daniel.kho 3762d 08h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/user.vhdl
16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 3865d 04h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/user.vhdl
15 [minor]: cleaned up sources. daniel.kho 3867d 11h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/user.vhdl
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 3876d 01h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/user.vhdl
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 3876d 06h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/user.vhdl
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 3887d 04h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/user.vhdl
9 Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. daniel.kho 3894d 01h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/user.vhdl

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