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Subversion Repositories bustap-jtag

[/] [bustap-jtag/] - Rev 25

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Rev Log message Author Age Path
25 Added AXI Passthrough Monitor IP for Vivado IP Integrator.
Can be synthesized by Vivado, but cannot be detected in the Vivado GUI.
Tk GUI can run with ISE/PLanahead 14.3 or 14.7.		 ash_riple 3518d 16h /bustap-jtag/
24 Added support for Qsys based avalon transaction monitoring. ash_riple 3538d 16h /bustap-jtag/
23 Updated Altera Tcl script to 32bit address bus. ash_riple 3745d 15h /bustap-jtag/
22 ash_riple 3745d 20h /bustap-jtag/
21 ash_riple 3745d 21h /bustap-jtag/
20 Added support for 32bit Address bus. ash_riple 3745d 21h /bustap-jtag/
19 Minor changes. ash_riple 4159d 16h /bustap-jtag/
18 Added support for Xilinx Chips.
Added support for AXI4-Lite bus. Can be used as an XPS IP.		 ash_riple 4159d 16h /bustap-jtag/
17 Added unreachable trigger condition "@WR & @RD" checking. ash_riple 4405d 19h /bustap-jtag/
16 Released version 2.2. ash_riple 4427d 20h /bustap-jtag/
15 Released version 2.2. ash_riple 4427d 20h /bustap-jtag/
14 Changed dec to hex value of triggerPnum. ash_riple 4428d 11h /bustap-jtag/
13 Added minor syntax changes and Linux environment simulation script. ash_riple 4428d 16h /bustap-jtag/
12 Added timing information to the capture content. ash_riple 4429d 00h /bustap-jtag/
11 Added pre-trigger capture. ash_riple 4429d 15h /bustap-jtag/
10 Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure. ash_riple 4434d 20h /bustap-jtag/
9 Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do".
Virtual JTAG stimulus can only be entered statically before simulation starts.
FIFO operation can be simulated dynamically while simulation is run.		 ash_riple 4435d 15h /bustap-jtag/
8 Added fault handling of wrong input length in the GUI. ash_riple 4439d 15h /bustap-jtag/
7 Added references related to "Bus Monitor". ash_riple 4439d 19h /bustap-jtag/
6 Updated to 2.1. New features added as in doc/Revision History.txt. ash_riple 4440d 15h /bustap-jtag/
5 Created code base for 2.x development.
Now supporting pipelined read/write access. Provided wrapper can be used as an example to connect up_monitor to any bus.		 ash_riple 4443d 16h /bustap-jtag/
4 Created tag for original source code. Version 1.0. ash_riple 4443d 18h /bustap-jtag/
3 Added original article. ash_riple 4443d 19h /bustap-jtag/
2 Checked in working code base. ash_riple 4447d 15h /bustap-jtag/
1 The project and the structure was created root 4448d 05h /bustap-jtag/

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