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Rev Log message Author Age Path
161 New directory structure. root 5550d 01h /can/tags/rel_18/
128 This commit was manufactured by cvs2svn to create tag 'rel_18'. 7537d 00h /tags/rel_18/
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7537d 00h /trunk/
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7537d 20h /trunk/
125 Synchronization changed, error counters fixed. mohor 7542d 02h /trunk/
124 ALTERA_RAM supported. mohor 7562d 08h /trunk/
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7569d 14h /trunk/
119 Artisan RAMs added. mohor 7578d 11h /trunk/
118 Artisan RAM fixed (when not using BIST). mohor 7578d 11h /trunk/
117 Tristate signal tx_o is separated to tx_o and tx_oen_o. Both signals need
to be joined together on higher level.		 mohor 7578d 11h /trunk/
115 Artisan ram instances added. simons 7584d 05h /trunk/
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7611d 06h /trunk/
111 Fixed according to the linter.
Case statement for data_out joined.		 mohor 7613d 06h /trunk/
110 Fixed according to the linter. mohor 7613d 06h /trunk/
109 Fixed according to the linter. mohor 7613d 07h /trunk/
108 Fixed according to the linter. mohor 7613d 07h /trunk/
107 Fixed according to the linter. mohor 7613d 08h /trunk/
106 Unused signal removed. mohor 7619d 05h /trunk/
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7619d 19h /trunk/
102 Little fixes (to fix warnings). mohor 7622d 10h /trunk/

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