URL https://opencores.org/ocsvn/cpu65c02_true_cycle/cpu65c02_true_cycle/trunk

Subversion Repositories cpu65c02_true_cycle

[/] [cpu65c02_true_cycle/] - Rev 22

Rev	Log message	Author	Age	Path
22	v1.52 PRODUCTION RESET generates SYNC now, 1 dead cycle delayed	fpga_is_funny	2078d 23h	/cpu65c02_true_cycle/
21		fpga_is_funny	2079d 20h	/cpu65c02_true_cycle/
20		fpga_is_funny	2079d 20h	/cpu65c02_true_cycle/
19		fpga_is_funny	3944d 01h	/cpu65c02_true_cycle/
18	RELEASE CANDIDATE V1.5 RC of r65c02_tc. Major Bug Fixes are available. Look at the header of r65c02_tc.vhd to get more details. Because of translation errors made by a third party conversion tool in the past, Verilog sources are no longer available. May be re-activated in the future. The upcoming PRODUCTION version will be include some enhancements for speed and resource utilization.	fpga_is_funny	3944d 02h	/cpu65c02_true_cycle/
17	Added old uploaded documents to new repository.	root	5549d 21h	/cpu65c02_true_cycle/
16	Added old uploaded documents to new repository.	root	5550d 13h	/cpu65c02_true_cycle/
15	New directory structure.	root	5550d 13h	/cpu65c02_true_cycle/