URL https://opencores.org/ocsvn/csa/csa/trunk

Subversion Repositories csa

[/] [csa/] - Rev 52

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Rev	Log message	Author	Age	Path
52	add the macro DEBUG_OUTPUT for the general debug information output	simon111	5143d 12h	/csa/
51	remove the using to iverilog and veriwell	simon111	5493d 14h	/csa/
50	add some documents	simon111	5494d 05h	/csa/
49	group_decrypt module simulate success	simon111	5500d 03h	/csa/
48	improve key_schedule module	simon111	5505d 02h	/csa/
47	add bin prepare function	simon111	5505d 05h	/csa/
46	delete key_comupter module and testbench	simon111	5505d 12h	/csa/
45	improve makefile	simon111	5507d 07h	/csa/
44	improve some module , strip warnings	simon111	5509d 02h	/csa/
43	improve group_decrypt module	simon111	5509d 04h	/csa/
42	add group_decrypt module	simon111	5509d 10h	/csa/
41	add three moudule ts_serial_out ts_sync key_cnt	simon111	5509d 23h	/csa/
40	add timescale.v file and fix a bug in key_schedule module	simon111	5510d 03h	/csa/
39	add usb controler module	simon111	5510d 07h	/csa/
38	improve the ledseg control module the register h must be 2bits width	simon111	5511d 01h	/csa/
37	improve write_data systemcall,	simon111	5511d 06h	/csa/
36	improve read_date vpi sytemcall, add offset and size argument	simon111	5511d 08h	/csa/
35	csa cli support binary test data	simon111	5511d 12h	/csa/
34	add binary test date (only sw_sim now )	simon111	5511d 14h	/csa/
33	improve ledseg controler module	simon111	5512d 02h	/csa/
32	fix a compile error	simon111	5512d 02h	/csa/
31	remove pc execute file	simon111	5512d 02h	/csa/
30	begin vailating on fpga	simon111	5512d 02h	/csa/
29	fix some bugs	simon111	5513d 02h	/csa/
28	create a quartus10 project for test the core	simon111	5513d 02h	/csa/
27	improve makefiles	simon111	5513d 14h	/csa/
26	Added old uploaded documents to new repository.	root	5549d 03h	/csa/
25	Added old uploaded documents to new repository.	root	5549d 19h	/csa/
24	New directory structure.	root	5549d 19h	/csa/

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Subversion Repositories csa

[/] [csa/] - Rev 52

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