OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_10/] - Rev 158

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
158 root 5551d 13h /dbg_interface/tags/rel_10/
76 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7516d 16h /tags/rel_10/
75 Simulation files. mohor 7516d 16h /trunk/
74 Removed. mohor 7516d 16h /trunk/
73 CRC logic changed. mohor 7516d 17h /trunk/
71 Mbist support added. simons 7518d 23h /trunk/
70 A pdf copy of existing doc document. simons 7526d 01h /trunk/
69 WBCNTL added, multiple CPU support described. simons 7546d 14h /trunk/
67 Lower two address lines must be always zero. simons 7551d 19h /trunk/
65 WB_CNTL register added, some syncronization fixes. simons 7552d 18h /trunk/
63 Three more chains added for cpu debug access. simons 7572d 19h /trunk/
61 Lapsus fixed. simons 7600d 19h /trunk/
59 Reset value for riscsel register set to 1. simons 7600d 19h /trunk/
57 Multiple cpu support added. simons 7600d 20h /trunk/
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7867d 17h /trunk/
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7867d 17h /trunk/
53 Trst active high. Inverted on higher layer. mohor 7867d 18h /trunk/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7867d 18h /trunk/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7895d 06h /trunk/
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 7895d 07h /trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.