URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] [eco32/] [trunk/] - Rev 333

Rev	Log message	Author	Age	Path
333	update TODO	hellwig	2743d 02h	/eco32/trunk/
332	update COPYING	hellwig	2804d 03h	/eco32/trunk/
331	machine monitor: init kbd and dsp only if explicitly requested	hellwig	2804d 16h	/eco32/trunk/
330	sim/getline/testgl.c: return type of main() changed to int	hellwig	2804d 17h	/eco32/trunk/
329	lcc/lburg/gram.y: prototype for yylex() added	hellwig	2804d 17h	/eco32/trunk/
328	lcc/etc/lcc.c: return type of main() changed to int	hellwig	2804d 17h	/eco32/trunk/
327	flag -m32 in compilation of vcdchk deleted	hellwig	3072d 03h	/eco32/trunk/
326	RAM simulation access times set to realistic values	hellwig	3182d 21h	/eco32/trunk/
325	memory speed measurement for new controller added	hellwig	3191d 13h	/eco32/trunk/
324	README updated	hellwig	3191d 13h	/eco32/trunk/
323	memspeed renamed to memspeed-1	hellwig	3191d 14h	/eco32/trunk/
322	README updated, Makefile added	hellwig	3192d 01h	/eco32/trunk/
321	README updated	hellwig	3192d 02h	/eco32/trunk/
320	README updated	hellwig	3192d 22h	/eco32/trunk/
319	memory controller 2, FPGA realization	hellwig	3193d 03h	/eco32/trunk/
318	memory controller 1, FPGA realization	hellwig	3193d 03h	/eco32/trunk/
317	README updated	hellwig	3193d 18h	/eco32/trunk/
316	README added	hellwig	3193d 21h	/eco32/trunk/
315	README added	hellwig	3193d 21h	/eco32/trunk/
314	memory controller simulation 2	hellwig	3193d 23h	/eco32/trunk/