URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

[/] - Rev 74

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Rev	Log message	Author	Age	Path
74	Added old uploaded documents to new repository.	root	5547d 11h	/
73	Added old uploaded documents to new repository.	root	5548d 03h	/
72	New directory structure.	root	5548d 03h	/
71	Replay xilinx fifo with private fifo	fisher5090	5882d 00h	/
70	no message	fisher5090	6545d 18h	/
69	no message	fisher5090	6545d 18h	/
68	datasheet of management module	fisher5090	6546d 04h	/
67	modify mgmt_miim_rdy timing sequence	fisher5090	6546d 12h	/
66	comments added	fisher5090	6546d 16h	/
65	bad coding style, but works, will be modified later	fisher5090	6546d 19h	/
64	no message	fisher5090	6549d 05h	/
63	remove pad function added, using xilinx vp20 -6 as target FPGA, passes post place and route simulation	fisher5090	6549d 05h	/
62	no message	fisher5090	6549d 12h	/
61	no message	fisher5090	6549d 14h	/
60	change rxd_in, rxc_in and rxclk_in signals'name to xgmii_rxd, xgmii_rxc and xgmii_rxclk	fisher5090	6549d 14h	/
59	first version	fisher5090	6549d 15h	/
58	configuration vector select inband fcs or not	fisher5090	6549d 20h	/
57	both inband fcs and no inband fcs are OK	fisher5090	6549d 20h	/
56	no message	fisher5090	6550d 12h	/
55	testbench for normal frame and error frame	fisher5090	6550d 12h	/
54	removed	fisher5090	6550d 12h	/
53	testbench for normal and error frame	fisher5090	6550d 17h	/
52	modified the rx_good_frame and rx_bad_frame timing sequence	fisher5090	6550d 17h	/
51	modified	fisher5090	6552d 20h	/
50	good version	fisher5090	6552d 20h	/
49	datasheet for receive module	fisher5090	6552d 20h	/
48	no message	fisher5090	6553d 12h	/
47	no message	fisher5090	6553d 16h	/
46	receive engine datasheet	fisher5090	6554d 05h	/
45	first version	fisher5090	6555d 14h	/

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Subversion Repositories ethmac10g

[/] - Rev 74

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