URL https://opencores.org/ocsvn/lq057q3dc02/lq057q3dc02/trunk

Subversion Repositories lq057q3dc02

[/] [lq057q3dc02/] [trunk/] - Rev 47

Rev	Log message	Author	Age	Path
47	New directory structure.	root	5549d 18h	/lq057q3dc02/trunk/
46	tested a new image, results are the same (i.e. works!)	jwdonal	5669d 13h	/trunk/
45	converted image to 72dpi	jwdonal	5672d 12h	/trunk/
44	converted to 72dpi	jwdonal	5672d 12h	/trunk/
43	updated for new top-level entity name	jwdonal	5672d 13h	/trunk/
42	deprecated!	jwdonal	5672d 13h	/trunk/
41	structural simulation models	jwdonal	5672d 13h	/trunk/
40	initial rev	jwdonal	5672d 13h	/trunk/
39	initial rev!	jwdonal	5672d 14h	/trunk/
38	updated for new Coregen BRAM version!	jwdonal	5672d 14h	/trunk/
37	new file to ignore!	jwdonal	5672d 17h	/trunk/
36	converted dcm_sys_to_lcd source file from verilog to VHDL so users don't have to have mixed-language simulation support. Aren't I so nice?? ;-)	jwdonal	5672d 17h	/trunk/
35	fixed spelling error	jwdonal	5672d 17h	/trunk/
34	fixed syntax	jwdonal	5672d 17h	/trunk/
33	added cvs edit feature	jwdonal	5672d 17h	/trunk/
32	initial rev	jwdonal	5672d 17h	/trunk/
31	moved to new location	jwdonal	5672d 17h	/trunk/
30	initial rev	jwdonal	5672d 18h	/trunk/
29	initial rev	jwdonal	5672d 18h	/trunk/
28	initial rev	jwdonal	5672d 19h	/trunk/