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URL https://opencores.org/ocsvn/lq057q3dc02/lq057q3dc02/trunk

Subversion Repositories lq057q3dc02

[/] [lq057q3dc02/] [trunk/] - Rev 47

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Rev Log message Author Age Path
47 New directory structure. root 5559d 11h /lq057q3dc02/trunk/
46 tested a new image, results are the same (i.e. works!) jwdonal 5679d 06h /trunk/
45 converted image to 72dpi jwdonal 5682d 05h /trunk/
44 converted to 72dpi jwdonal 5682d 05h /trunk/
43 updated for new top-level entity name jwdonal 5682d 06h /trunk/
42 deprecated! jwdonal 5682d 06h /trunk/
41 structural simulation models jwdonal 5682d 06h /trunk/
40 initial rev jwdonal 5682d 06h /trunk/
39 initial rev! jwdonal 5682d 07h /trunk/
38 updated for new Coregen BRAM version! jwdonal 5682d 07h /trunk/
37 new file to ignore! jwdonal 5682d 10h /trunk/
36 converted dcm_sys_to_lcd source file from verilog to VHDL so users don't have to have mixed-language simulation support. Aren't I so nice?? ;-) jwdonal 5682d 10h /trunk/
35 fixed spelling error jwdonal 5682d 10h /trunk/
34 fixed syntax jwdonal 5682d 10h /trunk/
33 added cvs edit feature jwdonal 5682d 10h /trunk/
32 initial rev jwdonal 5682d 10h /trunk/
31 moved to new location jwdonal 5682d 10h /trunk/
30 initial rev jwdonal 5682d 11h /trunk/
29 initial rev jwdonal 5682d 11h /trunk/
28 initial rev jwdonal 5682d 12h /trunk/
27 comments jwdonal 5990d 05h /trunk/
26 *** empty log message *** jwdonal 6197d 03h /trunk/
25 *** empty log message *** jwdonal 6197d 03h /trunk/
24 Fixed order of operations jwdonal 6197d 04h /trunk/
23 Added note on changing project directory names. jwdonal 6197d 04h /trunk/
22 New source files directory. jwdonal 6197d 04h /trunk/
21 Changed source files directory name. Necessary for proper simulation results do to XCO files remembering the COE file search path. jwdonal 6197d 04h /trunk/
20 Changed coefficiecint (COE) files search path jwdonal 6197d 04h /trunk/
19 *** empty log message *** jwdonal 6197d 04h /trunk/
18 Modified coefficient files search path. jwdonal 6197d 05h /trunk/

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