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URL https://opencores.org/ocsvn/manchesterwireless/manchesterwireless/trunk

Subversion Repositories manchesterwireless

[/] [manchesterwireless/] - Rev 16

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Rev Log message Author Age Path
16 Removed useless code kingmu 5409d 08h /manchesterwireless/
15 Replaced with more advanced version created by Thiagarajan kingmu 5412d 11h /manchesterwireless/
14 Removed Xilinx warning caused by missing signals in sensitivity list kingmu 5412d 11h /manchesterwireless/
13 Merged rewrite of singleDouble into trunk kingmu 5413d 09h /manchesterwireless/
12 Trivial updates kingmu 5419d 15h /manchesterwireless/
11 This is a perl model which functionally simulates manchester encoding and decoding. thiagu_comp 5421d 01h /manchesterwireless/
10 This folder contains the perl model, which functionally simulates manchester encoding and decoding. This can be used to validate the HDL model. thiagu_comp 5421d 01h /manchesterwireless/
9 Modified next state logic to avoid gated clock on net clock_zero_en_0000 during bitgen process. As a default case the counter enables are de-asserted. thiagu_comp 5424d 02h /manchesterwireless/
8 Removed old singleDouble and added .ucf kingmu 5427d 04h /manchesterwireless/
7 Added new singleDouble files kingmu 5427d 04h /manchesterwireless/
6 Branching trunk to experiment with new singleDouble module kingmu 5427d 05h /manchesterwireless/
5 Tagging 1.0 release kingmu 5427d 14h /manchesterwireless/
4 Updated simulation files to reflect new module names kingmu 5432d 09h /manchesterwireless/
3 Renamed files/modules. Added documentation. kingmu 5432d 09h /manchesterwireless/
2 initial commit kingmu 5433d 10h /manchesterwireless/
1 The project was created and the structure was created root 5440d 01h /manchesterwireless/

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