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[/] [mdct/] [tags/] [MDCT_REL_B1_8/] - Rev 24

Rev	Log message	Author	Age	Path
24	New directory structure.	root	5547d 20h	/mdct/tags/MDCT_REL_B1_8/
23	This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_8'.		5550d 02h	/tags/MDCT_REL_B1_8/
22	project released under LGPL	mikel262	5550d 02h	/trunk/
21	Fix for XST synthesis error and improve readibility (by Andreas Bergmann).	mikel262	5550d 03h	/trunk/
20	Fix for XST synthesis error and improve readibility (by Andreas Bergman).	mikel262	5550d 03h	/trunk/
18	Minor fixes. This release is FPGA proven.	mikel262	6574d 23h	/trunk/
16	Documentation update, minor fixes	mikel262	6596d 20h	/trunk/
15	Redesigned. Fully pipelined, always ready for data design	mikel262	6596d 21h	/trunk/
13	performance improved by 8%, latency reduced to 94 cycles	mikel262	6600d 20h	/trunk/
11	changed ROM memory model to synchronous	mikel262	6601d 19h	/trunk/
10	+ moved memory allocation request to where it should be + reduced latency to 104 cycles	mikel262	6602d 21h	/trunk/
8	Updated DOC	mikel262	6605d 08h	/trunk/
7	documentation update. minor area optimization.	mikel262	6605d 19h	/trunk/
6	minor updates	mikel262	6606d 19h	/trunk/
4	area optimization - 100 slices less	mikel262	6606d 20h	/trunk/
2	Initial import (Beta Release)	mikel262	6607d 08h	/trunk/
1	Standard project directories initialized by cvs2svn.		6607d 08h	/trunk/