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Rev Log message Author Age Path
28 updated doc mikel262 5525d 10h /mdct/trunk/
27 Inserted multiple stage pipeline for final adders to improve greatly performance with expense of area. mikel262 5525d 10h /mdct/trunk/
24 New directory structure. root 5533d 05h /mdct/trunk/
22 project released under LGPL mikel262 5535d 11h /trunk/
21 Fix for XST synthesis error and improve readibility (by Andreas Bergmann). mikel262 5535d 12h /trunk/
20 Fix for XST synthesis error and improve readibility (by Andreas Bergman). mikel262 5535d 12h /trunk/
18 Minor fixes. This release is FPGA proven. mikel262 6560d 08h /trunk/
16 Documentation update, minor fixes mikel262 6582d 04h /trunk/
15 Redesigned. Fully pipelined, always ready for data design mikel262 6582d 05h /trunk/
13 performance improved by 8%, latency reduced to 94 cycles mikel262 6586d 04h /trunk/
11 changed ROM memory model to synchronous mikel262 6587d 04h /trunk/
10 + moved memory allocation request to where it should be
+ reduced latency to 104 cycles
mikel262 6588d 06h /trunk/
8 Updated DOC mikel262 6590d 17h /trunk/
7 documentation update. minor area optimization. mikel262 6591d 03h /trunk/
6 minor updates mikel262 6592d 04h /trunk/
4 area optimization - 100 slices less mikel262 6592d 05h /trunk/
2 Initial import (Beta Release) mikel262 6592d 17h /trunk/
1 Standard project directories initialized by cvs2svn. 6592d 17h /trunk/

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