URL https://opencores.org/ocsvn/next186/next186/trunk

Subversion Repositories next186

[/] [next186/] [trunk/] [Next186_CPU.v] - Rev 20

Rev	Log message	Author	Age	Path
20	Implemented the undocumented SALC instructions (SBB AL, AL without affecting the flags) Some speed improvements (separate data/address I/O path)	ndumitrache	2440d 02h	/next186/trunk/Next186_CPU.v
19	Add A20 address line	ndumitrache	3660d 23h	/next186/trunk/Next186_CPU.v
14	generate invalid opcode exception for MOV FS and GS	ndumitrache	4013d 17h	/next186/trunk/Next186_CPU.v
13	fix PUSHA SP pushed stack value, which should be the one before PUSHA	ndumitrache	4022d 03h	/next186/trunk/Next186_CPU.v
12	fix IDIV when Q=0	ndumitrache	4056d 20h	/next186/trunk/Next186_CPU.v
11	fix RET n alignment bug fix TRAP interrupt acknowledge updated specs	ndumitrache	4064d 03h	/next186/trunk/Next186_CPU.v
10	fixed MUL/IMUL 8bit flags bug	ndumitrache	4100d 20h	/next186/trunk/Next186_CPU.v
8	fixed DIV bug (exception on sign bit)	ndumitrache	4162d 22h	/next186/trunk/Next186_CPU.v
7	fixed REP CMPS/SCAS bug when interrupted on the <equal> item	ndumitrache	4387d 04h	/next186/trunk/Next186_CPU.v
5	Fixed CMPS/SCAS bug when interrupted on the <equal> item	ndumitrache	4387d 05h	/next186/trunk/Next186_CPU.v
3	updated comments	ndumitrache	4452d 04h	/next186/trunk/Next186_CPU.v
2	v1.0	ndumitrache	4452d 21h	/next186/trunk/Next186_CPU.v