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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_clock_mux.v] - Rev 205

Rev	Log message	Author	Age	Path
205	Thanks again to Johan W. good feedback, the following updates are implemented: - Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment. - Update oscillators enable generation to relax a critical timing paths in the ASIC version. - Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).	olivier.girard	3230d 08h	/openmsp430/trunk/core/rtl/verilog/omsp_clock_mux.v
202	Add DMA interface support + LINT cleanup	olivier.girard	3244d 08h	/openmsp430/trunk/core/rtl/verilog/omsp_clock_mux.v
134	Add full ASIC support (low-power modes, DFT, ...). Improved serial debug interface reliability.	olivier.girard	4440d 09h	/openmsp430/trunk/core/rtl/verilog/omsp_clock_mux.v