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Rev Log message Author Age Path
145 Add Dhrystone and CoreMark benchmarks to the simulation environment. olivier.girard 4371d 09h /
144 Update ChangeLog olivier.girard 4392d 10h /
143 Update FPGA software examples to support MSPGCC Uniarch. olivier.girard 4392d 10h /
142 Beautify the linker script examples. olivier.girard 4392d 10h /
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 4396d 09h /
140 Update ChangeLog olivier.girard 4408d 10h /
139 Add some SVN ignore patterns olivier.girard 4408d 19h /
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4408d 19h /
137 Update ChangeLog olivier.girard 4440d 09h /
136 Update all FPGA projects with the latest core version. olivier.girard 4440d 09h /
135 Update documentation to reflect the ASIC implementation options. olivier.girard 4440d 09h /
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4440d 09h /
133 Add support for new CPU version. olivier.girard 4440d 09h /
132 Update FPGA examples with the POP.B bug fix olivier.girard 4453d 09h /
131 Update ChangeLog olivier.girard 4461d 08h /
130 Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) olivier.girard 4461d 08h /
129 Update ChangeLog olivier.girard 4537d 09h /
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4537d 09h /
127 update changelog... olivier.girard 4573d 08h /
126 Remove freewrap642 directory.
Tools users now have to install TCL/TK instead.		 olivier.girard 4573d 08h /

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