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353 OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.

ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""

or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)

ORPmon play around, various changes to low level files.		 julius 5002d 23h /openrisc/
352 OR1200 RTL DC sensitivity list fix julius 5003d 20h /openrisc/
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 5003d 20h /openrisc/
350 Adding new OR1200 processor to ORPSoCv2 julius 5004d 00h /openrisc/
349 ORPSoCv2 update with new software and makefile update julius 5004d 00h /openrisc/
348 First stage of ORPSoCv2 update - more to come julius 5004d 01h /openrisc/
347 Tagging the 0.5.0rc1 candidate release of Or1ksim. jeremybennett 5004d 02h /openrisc/
346 Changes to support Or1ksim 0.5.0rc1

Top level changes:

* config.h.in: Regenerated.
* debug.cfg, rsp.cfg: Deleted.
* doc/or1ksim.texi: Updated for new options and library interface.
* doc/or1ksim.info, doc/version.texi: Regenerated.
* Makefile.am: Added sim.cfg to EXTRA_DIST.
* NEWS: Updated for 0.5.0rc1.
* or1ksim.h <enum or1ksim_rc>: OR1KSIM_RC_OK explicitly zero.
* sim.cfg: Updated for consistency with the user guide.
* sim-config.c (init_defconfig): 50000 as default VAPI port.
(alloc_memory_block): Verbose message of amount allocated.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.

Changes in testsuite:

* libsim.tests/int-edge.exp <int-edge simple 1>: Increase time
between interrupts to 2ms.
<int-edge simple 2>: Increase time between interrupts to 2ms.
<int-edge duplicated 1>: Increase time between interrupts to 2ms.
<int-edge duplicated 2>: Increase time between interrupts to 2ms.

Changes in testsuite/test-code-or1k:

* mc-common/except-mc.S: Remove leading underscores from global
symbols.
* except/except.S: Remove leading underscores from global symbols.
* cache/cache-asm.S: Remove leading underscores from global symbols.
* cache/cache.c (jump_and_link): Remove leading underscore from
label.
(jump): Remove leading underscore from label.
(all): Remove leading underscore from global symbol references.
* testfloat/systfloat.S: Remove leading underscores from global
symbols.
* mmu/mmu.c (jump): Remove leading underscore from label.
* mmu/mmu-asm.S: Remove leading underscores from global symbols.
* except-test/except-test.c: Remove leading underscores from
global symbols.
* except-test/except-test-s.S: Remove leading underscores from
global symbols.
* uos/except-or32.S: Remove leading underscores from global
symbols.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.		 jeremybennett 5004d 02h /openrisc/
345 Tagging the 1.0rc1 candidate release of Newlib 1.18.0 jeremybennett 5004d 21h /openrisc/
344 Directory for tagging newlib 1.18.0 jeremybennett 5004d 21h /openrisc/
343 Build C++ and its libraries. jeremybennett 5004d 23h /openrisc/
342 Various files regenerated as part of RC1 creation. jeremybennett 5004d 23h /openrisc/
341 Tagging the 1.0rc1 candidate release of GDB 7.2 jeremybennett 5005d 01h /openrisc/
340 Tag directory for GDB 7.2. jeremybennett 5005d 01h /openrisc/
339 Updates for GDB 7.2 for OpenRISC version 1.0 release candidate 1. OpenRISC
documentation subsumes the old separate OpenRISC document.		 jeremybennett 5005d 04h /openrisc/
338 Tagging the 1.0rc1 candidate release of GCC 4.5.1 jeremybennett 5005d 20h /openrisc/
337 Directory for GCC 4.5.1 tags jeremybennett 5005d 20h /openrisc/
336 Corrected for 4.5.1-or32-1.0rc1 jeremybennett 5005d 21h /openrisc/
335 Updated version number to 4.5.1-or32-1.0. jeremybennett 5005d 21h /openrisc/
334 Record changes to the documentation and option handling. jeremybennett 5005d 21h /openrisc/

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