OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 851

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
851 changed branch delay flags skrzyp 4209d 00h /openrisc/trunk/
850 or1200_genpc: fix ipcu_cycstb_o generation

In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).

This fixes this issue.

Patch by: Franck Jullien <franck.jullien@gmail.com>		 stekern 4220d 16h /openrisc/trunk/
849 or1200: Fix for cache bug related to first_{hit|miss}_ack

Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.

Patch by: Matthew Hicks <firefalcon@gmail.com>		 stekern 4220d 16h /openrisc/trunk/
848 or1200: l.lws support

Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.

Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk>		 stekern 4220d 16h /openrisc/trunk/
847 or1200_genpc: fix ipcu_cycstb_o generation

In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).

This fixes this issue.

Patch by: Franck Jullien <franck.jullien@gmail.com>		 stekern 4220d 16h /openrisc/trunk/
846 or1200: Fix for cache bug related to first_{hit|miss}_ack

Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.

Patch by: Matthew Hicks <firefalcon@gmail.com>		 stekern 4220d 16h /openrisc/trunk/
845 or1200: l.lws support

Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.

Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk>		 stekern 4220d 16h /openrisc/trunk/
844 skrzyp 4221d 09h /openrisc/trunk/
843 Applied RDiez suggestions skrzyp 4221d 09h /openrisc/trunk/
842 Moving GDB 7.1 into the old collection. jeremybennett 4223d 07h /openrisc/trunk/
841 GDB 7.2 is now considered the stable version. jeremybennett 4223d 08h /openrisc/trunk/
840 Relocate GDB 6.8 to the old directory. jeremybennett 4223d 08h /openrisc/trunk/
839 Forgot about updating linker flags, thanks RDiez! skrzyp 4224d 11h /openrisc/trunk/
838 added branch-delay option and sets r0 to zero skrzyp 4225d 00h /openrisc/trunk/
837 Instructions redirecting users to new directories. jeremybennett 4231d 05h /openrisc/trunk/
836 The old legacy directory, which just a README these days. jeremybennett 4231d 06h /openrisc/trunk/
835 Move current version to stable directory. jeremybennett 4231d 06h /openrisc/trunk/
834 Move current version to stable directory. jeremybennett 4231d 06h /openrisc/trunk/
833 Move current version to stable directory. jeremybennett 4231d 06h /openrisc/trunk/
832 Move current version to stable directory. jeremybennett 4231d 06h /openrisc/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.