OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1ksim/] [Makefile.in] - Rev 784

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
784 Patch from R Diez to ensure DejaGnu handles errors better. Autoconf infrastructure all updated.

2012-03-21 Jeremy Bennett <jeremy.bennett@embecosm.com>

Patch from R Diez <rdiezmail-openrisc@yahoo.de>

* Makefile.am: Add AM_RUNTESTFLAGS to trigger correct error
behaviour.
jeremybennett 4424d 19h /openrisc/trunk/or1ksim/Makefile.in
625 Fixed configuration to work with GCC 4.6, added -Werror to avoid GCC 4.6 warning as a temporary fix. Added pic.cfg to EXTRA_DIST. Made tests build with SILENT_RULES if available. jeremybennett 4644d 02h /openrisc/trunk/or1ksim/Makefile.in
556 or1ksim - added performance counters unit and test for it. julius 4713d 19h /openrisc/trunk/or1ksim/Makefile.in
538 or1ksim updates. spr-def.h updates, Cygwin compile error fixes. julius 4741d 23h /openrisc/trunk/or1ksim/Makefile.in
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 4866d 04h /openrisc/trunk/or1ksim/Makefile.in
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 4875d 23h /openrisc/trunk/or1ksim/Makefile.in
440 Updated documentation to describe new Ethernet usage. jeremybennett 4893d 18h /openrisc/trunk/or1ksim/Makefile.in
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 4902d 13h /openrisc/trunk/or1ksim/Makefile.in
432 Updates to handle interrupts correctly. jeremybennett 4906d 23h /openrisc/trunk/or1ksim/Makefile.in
428 or1ksim - adding preliminary PHY emulation to ethernet peripheral. julius 4912d 18h /openrisc/trunk/or1ksim/Makefile.in
346 Changes to support Or1ksim 0.5.0rc1

Top level changes:

* config.h.in: Regenerated.
* debug.cfg, rsp.cfg: Deleted.
* doc/or1ksim.texi: Updated for new options and library interface.
* doc/or1ksim.info, doc/version.texi: Regenerated.
* Makefile.am: Added sim.cfg to EXTRA_DIST.
* NEWS: Updated for 0.5.0rc1.
* or1ksim.h <enum or1ksim_rc>: OR1KSIM_RC_OK explicitly zero.
* sim.cfg: Updated for consistency with the user guide.
* sim-config.c (init_defconfig): 50000 as default VAPI port.
(alloc_memory_block): Verbose message of amount allocated.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.

Changes in testsuite:

* libsim.tests/int-edge.exp <int-edge simple 1>: Increase time
between interrupts to 2ms.
<int-edge simple 2>: Increase time between interrupts to 2ms.
<int-edge duplicated 1>: Increase time between interrupts to 2ms.
<int-edge duplicated 2>: Increase time between interrupts to 2ms.

Changes in testsuite/test-code-or1k:

* mc-common/except-mc.S: Remove leading underscores from global
symbols.
* except/except.S: Remove leading underscores from global symbols.
* cache/cache-asm.S: Remove leading underscores from global symbols.
* cache/cache.c (jump_and_link): Remove leading underscore from
label.
(jump): Remove leading underscore from label.
(all): Remove leading underscore from global symbol references.
* testfloat/systfloat.S: Remove leading underscores from global
symbols.
* mmu/mmu.c (jump): Remove leading underscore from label.
* mmu/mmu-asm.S: Remove leading underscores from global symbols.
* except-test/except-test.c: Remove leading underscores from
global symbols.
* except-test/except-test-s.S: Remove leading underscores from
global symbols.
* uos/except-or32.S: Remove leading underscores from global
symbols.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.
jeremybennett 4986d 02h /openrisc/trunk/or1ksim/Makefile.in
236 Terminate execution on NOP_EXIT, even if debugging, add support for RSP qAttached packet, stall in library after single instruction is ST bit is set in SPR DMR1. Fix softfloat to allow compilation with -O0 for debugging.

* configure: Regenerated.
* configure.ac: Version changed to current date. Test for
varargs.h dropped.
* cpu/or32/insnset.c <l_nop>: Terminate execution on NOP_EXIT,
even if debugging.
* debug/rsp-server.c (rsp_query): Added support for qAttached
packet.
* libtoplevel.c (or1ksim_run): Stall after a single instruction if
SPR_DMR1_ST flag is set.
* softfloat/host.h: Make #define of INLINE conditional, to allow
the user to override.
* softfloat/README: Added instructions for non-optimized compilation.
* softfloat/softfloat-macros: Add a conditional #ifndef
NO_SOFTFLOAT_UNUSUED around unused functions.
jeremybennett 5019d 22h /openrisc/trunk/or1ksim/Makefile.in
235 Removed support for old OpenRISC JTAG Remote Protocol. jeremybennett 5020d 02h /openrisc/trunk/or1ksim/Makefile.in
234 Minor tidy ups. DOS end of line chars fixed. jeremybennett 5021d 04h /openrisc/trunk/or1ksim/Makefile.in
233 New softfloat FPU and testfloat sw for or1ksim julius 5021d 15h /openrisc/trunk/or1ksim/Makefile.in
230 Changed library interface. Fixed namespace problems with instruction lookup in library.

* configure: Regenerated.
* configure.ac: Version changed to current date.
* cpu/or1k/opcode/or32.h <or1ksim_build_automata>: Renamed from
build_automata.
<l_none, num_opcodes, insn_index>: Deleted.
<or1ksim_op_start>: Renamed from op_start.
<or1ksim_automata>: Renamed from automata.
<or1ksim_ti>: Renamed from ti.
<or1ksim_or32_opcodes>: Renamed from or32_opcodes.
<or1ksim_disassembled>: Renamed from disassembled.
<or1ksim_insn_len>: Renamed from insn_len.
<or1ksim_insn_name>: Renamed from insn_name.
<or1ksim_destruct_automata>: Renamed from destruct_automata.
<or1ksim_insn_decode>: Renamed from insn_decode.
<or1ksim_disassemble_insn>: Renamed from disassemble_insn.
<or1ksim_disassemble_index>: Renamed from disassemble_index.
<or1ksim_extend_imm>: Renamed from extend_imm.
<or1ksim_or32_extract>: Renamed from or32_extract
* cpu/or32/or32.c, cpu/or32/execute.c, cpu/or32/generate.c,
* cpu/common/stats.c, cpu/common/abstract.c, cpu/common/parse.c,
* cpu/or1k/opcode/or32.h, cuc/load.c, cuc/cuc.c,
* support/dumpverilog.c, toplevel-support.c: Renaming
corresponding to changes in cpu/or1k/opcode/or32.h.
* cpu/or32/execute-fp.h: Deleted
* cpu/or32/generate.c <include_strings>: Remove reference to
execute-fp.h
* cpu/or32/execute.c <host_fp_rm>: Declared static.
(fp_set_flags_restore_host_rm, fp_set_or1k_rm): Declared static,
forward declaration removed.
* or1ksim.h (or1ksim_read_mem, or1ksim_write_mem): addr arg
changed to unsigned long int.
(or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
(or1ksim_write_spr): sprval arg changed to unsigned long int.
(or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
(or1ksim_write_reg): regval arg changed to unsigned long int.
* libtoplevel.c (or1ksim_read_mem, or1ksim_write_mem): addr arg
changed to unsigned long int.
(or1ksim_read_spr): sprval_ptr arg changed to unsigned long int *.
(or1ksim_write_spr): sprval arg changed to unsigned long int.
(or1ksim_read_reg): regval_ptr arg changed to unsigned long int *.
(or1ksim_write_reg): regval arg changed to unsigned long int.
jeremybennett 5022d 20h /openrisc/trunk/or1ksim/Makefile.in
226 Orksim floating point support additions, spr-defs.h updates, newlib cache init routines updated julius 5024d 20h /openrisc/trunk/or1ksim/Makefile.in
121 Adds exception handling to l.jalr and l.jr. Adds appropriate tests. jeremybennett 5070d 20h /openrisc/trunk/or1ksim/Makefile.in
118 New tests of multiply. Improved tests of exception handling for addition and division. Improvements to instruction testing library. jeremybennett 5071d 17h /openrisc/trunk/or1ksim/Makefile.in
101 ChangeLog updated for floating point support. Fixed bug in generic peripheral upcalls. Upped release date in configure.ac. Removed redundant debugging print in abstract.c jeremybennett 5090d 22h /openrisc/trunk/or1ksim/Makefile.in

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.