| Rev |
Log message |
Author |
Age |
Path |
| 787 |
Patch from R Diez to zero R0 on startup. ChangeLog from testsuite/test-code-or1k:
2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com>
Patch from R Diez <rdiezmail-openrisc@yahoo.de>
* cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S,
* except/except.S, ext/ext.S, flag/flag.S, fp/fp.S,
* inst-set-test/inst-set-test.S, int-test/int-test.S,
* mc-common/except-mc.S, uos/except-or32.S: Clear R0 on
start-up. There is no guarantee that R0 is hardwired to zero, and
indeed it is not when simulating the or1200 Verilog core.
* configure: Regenerated.
* configure.ac: Updated version. |
jeremybennett |
4438d 10h |
/openrisc/trunk/or1ksim/configure.ac |
| 784 |
Patch from R Diez to ensure DejaGnu handles errors better. Autoconf infrastructure all updated.
2012-03-21 Jeremy Bennett <jeremy.bennett@embecosm.com>
Patch from R Diez <rdiezmail-openrisc@yahoo.de>
* Makefile.am: Add AM_RUNTESTFLAGS to trigger correct error
behaviour. |
jeremybennett |
4440d 00h |
/openrisc/trunk/or1ksim/configure.ac |
| 625 |
Fixed configuration to work with GCC 4.6, added -Werror to avoid GCC 4.6 warning as a temporary fix. Added pic.cfg to EXTRA_DIST. Made tests build with SILENT_RULES if available. |
jeremybennett |
4659d 08h |
/openrisc/trunk/or1ksim/configure.ac |
| 569 |
Added AM_SILENT_RULES for nicer builds |
olof |
4697d 04h |
/openrisc/trunk/or1ksim/configure.ac |
| 556 |
or1ksim - added performance counters unit and test for it. |
julius |
4729d 00h |
/openrisc/trunk/or1ksim/configure.ac |
| 552 |
or1ksim - cpu/ cleanup - remove dynamic execution model WIP, and dlx, or16 targets |
julius |
4730d 09h |
/openrisc/trunk/or1ksim/configure.ac |
| 538 |
or1ksim updates. spr-def.h updates, Cygwin compile error fixes. |
julius |
4757d 05h |
/openrisc/trunk/or1ksim/configure.ac |
| 532 |
Ensure the halted flag is cleared when the processor is unstalled. |
jeremybennett |
4768d 01h |
/openrisc/trunk/or1ksim/configure.ac |
| 510 |
Updates for release 0.5.1rc1. |
jeremybennett |
4788d 09h |
/openrisc/trunk/or1ksim/configure.ac |
| 508 |
Updates for Or1ksim 0.5.0rc3. |
jeremybennett |
4789d 09h |
/openrisc/trunk/or1ksim/configure.ac |
| 494 |
Change to ensure handles ctrl-C correctly with empty line. |
jeremybennett |
4831d 02h |
/openrisc/trunk/or1ksim/configure.ac |
| 483 |
Updated with new opcodes to generate random numbers and to identify us as Or1ksim. |
jeremybennett |
4854d 10h |
/openrisc/trunk/or1ksim/configure.ac |
| 460 |
Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. |
jeremybennett |
4881d 10h |
/openrisc/trunk/or1ksim/configure.ac |
| 450 |
Simplified (and hopefully more reliable) Ethernet MAC/PHY. |
jeremybennett |
4902d 04h |
/openrisc/trunk/or1ksim/configure.ac |
| 440 |
Updated documentation to describe new Ethernet usage. |
jeremybennett |
4909d 00h |
/openrisc/trunk/or1ksim/configure.ac |
| 434 |
Work in progress with new Ethernet TUN/TAP interface. |
jeremybennett |
4921d 01h |
/openrisc/trunk/or1ksim/configure.ac |
| 432 |
Updates to handle interrupts correctly. |
jeremybennett |
4922d 04h |
/openrisc/trunk/or1ksim/configure.ac |
| 420 |
New feature to trace instructions (option --trace). Manual updated to match. |
jeremybennett |
4936d 05h |
/openrisc/trunk/or1ksim/configure.ac |
| 387 |
Fixed testing, to always use our DEJAGNU config. |
jeremybennett |
4976d 05h |
/openrisc/trunk/or1ksim/configure.ac |
| 385 |
Updates for Or1ksim 0.5.0rc2.
* configure: Regenerated.
* configure.ac: Minor tidy ups. Version changed to 0.5.0rc2.
* debug/rsp-server.c (rsp_query): Simplified handling of
"qTStatus" to indicate we just do not support tracing.
* doc/or1ksim.texi <Configuring the Build>: No longer mandatory to
specify the target.
<Memory Configuration>: Warns about issues with memory controller.
<Memory Controller Configuration>: Warns about issues with memory
controller and advises not to use it.
<Standalone Simulator>: Details for options with arguments updated.
* NEWS: Updated for 0.5.0rc2.
* peripheral/mc.c (mc_poc): Use constant MC_POC_VALID
(mc_index): Ensure value is valid.
* peripheral/mc-defines.h <MC_CE_VALID>: Defined.
* testsuite/test-code-or1k/configure: Regenerated.
* testsuite/test-code-or1k/configure.ac: Handle the case where
target_cpu is not set. Version changed to 0.5.0rc2.
* testsuite/test-code-or1k/support/spr-defs.h <SPR_VR_RES>:
Definition corrected. |
jeremybennett |
4976d 05h |
/openrisc/trunk/or1ksim/configure.ac |
