| Rev |
Log message |
Author |
Age |
Path |
| 787 |
Patch from R Diez to zero R0 on startup. ChangeLog from testsuite/test-code-or1k:
2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com>
Patch from R Diez <rdiezmail-openrisc@yahoo.de>
* cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S,
* except/except.S, ext/ext.S, flag/flag.S, fp/fp.S,
* inst-set-test/inst-set-test.S, int-test/int-test.S,
* mc-common/except-mc.S, uos/except-or32.S: Clear R0 on
start-up. There is no guarantee that R0 is hardwired to zero, and
indeed it is not when simulating the or1200 Verilog core.
* configure: Regenerated.
* configure.ac: Updated version. |
jeremybennett |
4440d 11h |
/openrisc/trunk/or1ksim/doc/ |
| 784 |
Patch from R Diez to ensure DejaGnu handles errors better. Autoconf infrastructure all updated.
2012-03-21 Jeremy Bennett <jeremy.bennett@embecosm.com>
Patch from R Diez <rdiezmail-openrisc@yahoo.de>
* Makefile.am: Add AM_RUNTESTFLAGS to trigger correct error
behaviour. |
jeremybennett |
4442d 02h |
/openrisc/trunk/or1ksim/doc/ |
| 625 |
Fixed configuration to work with GCC 4.6, added -Werror to avoid GCC 4.6 warning as a temporary fix. Added pic.cfg to EXTRA_DIST. Made tests build with SILENT_RULES if available. |
jeremybennett |
4661d 09h |
/openrisc/trunk/or1ksim/doc/ |
| 561 |
or1ksim - timer module, spr-defs.h re-bugfix |
julius |
4725d 08h |
/openrisc/trunk/or1ksim/doc/ |
| 556 |
or1ksim - added performance counters unit and test for it. |
julius |
4731d 02h |
/openrisc/trunk/or1ksim/doc/ |
| 552 |
or1ksim - cpu/ cleanup - remove dynamic execution model WIP, and dlx, or16 targets |
julius |
4732d 10h |
/openrisc/trunk/or1ksim/doc/ |
| 538 |
or1ksim updates. spr-def.h updates, Cygwin compile error fixes. |
julius |
4759d 06h |
/openrisc/trunk/or1ksim/doc/ |
| 510 |
Updates for release 0.5.1rc1. |
jeremybennett |
4790d 10h |
/openrisc/trunk/or1ksim/doc/ |
| 508 |
Updates for Or1ksim 0.5.0rc3. |
jeremybennett |
4791d 10h |
/openrisc/trunk/or1ksim/doc/ |
| 494 |
Change to ensure handles ctrl-C correctly with empty line. |
jeremybennett |
4833d 03h |
/openrisc/trunk/or1ksim/doc/ |
| 483 |
Updated with new opcodes to generate random numbers and to identify us as Or1ksim. |
jeremybennett |
4856d 12h |
/openrisc/trunk/or1ksim/doc/ |
| 472 |
Various changes which improve the quality of the tracing. |
jeremybennett |
4875d 13h |
/openrisc/trunk/or1ksim/doc/ |
| 460 |
Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. |
jeremybennett |
4883d 11h |
/openrisc/trunk/or1ksim/doc/ |
| 457 |
or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. |
julius |
4893d 06h |
/openrisc/trunk/or1ksim/doc/ |
| 451 |
More tidying up. |
jeremybennett |
4904d 02h |
/openrisc/trunk/or1ksim/doc/ |
| 450 |
Simplified (and hopefully more reliable) Ethernet MAC/PHY. |
jeremybennett |
4904d 06h |
/openrisc/trunk/or1ksim/doc/ |
| 443 |
Work in progress on more efficient Ethernet. |
jeremybennett |
4909d 10h |
/openrisc/trunk/or1ksim/doc/ |
| 442 |
OR1Ksim - adding trace controlability by SIGUSR1 signal. |
julius |
4910d 00h |
/openrisc/trunk/or1ksim/doc/ |
| 440 |
Updated documentation to describe new Ethernet usage. |
jeremybennett |
4911d 02h |
/openrisc/trunk/or1ksim/doc/ |
| 436 |
Or1ksim ethernet TAP updates. Ethernet test still failing. |
julius |
4919d 20h |
/openrisc/trunk/or1ksim/doc/ |
| 434 |
Work in progress with new Ethernet TUN/TAP interface. |
jeremybennett |
4923d 02h |
/openrisc/trunk/or1ksim/doc/ |
| 432 |
Updates to handle interrupts correctly. |
jeremybennett |
4924d 06h |
/openrisc/trunk/or1ksim/doc/ |
| 430 |
or1ksim - clarifying interrupt behavior in code and documentation. |
julius |
4927d 02h |
/openrisc/trunk/or1ksim/doc/ |
| 429 |
or1ksim update - remove debug printfs from eth MDIO emulation function
and fix illegal instruction vector jump for invalid instructions. |
julius |
4927d 06h |
/openrisc/trunk/or1ksim/doc/ |
| 428 |
or1ksim - adding preliminary PHY emulation to ethernet peripheral. |
julius |
4930d 02h |
/openrisc/trunk/or1ksim/doc/ |
| 420 |
New feature to trace instructions (option --trace). Manual updated to match. |
jeremybennett |
4938d 06h |
/openrisc/trunk/or1ksim/doc/ |
| 418 |
Or1ksim - adding new option when configuring memories, "exitnops" |
julius |
4938d 09h |
/openrisc/trunk/or1ksim/doc/ |
| 385 |
Updates for Or1ksim 0.5.0rc2.
* configure: Regenerated.
* configure.ac: Minor tidy ups. Version changed to 0.5.0rc2.
* debug/rsp-server.c (rsp_query): Simplified handling of
"qTStatus" to indicate we just do not support tracing.
* doc/or1ksim.texi <Configuring the Build>: No longer mandatory to
specify the target.
<Memory Configuration>: Warns about issues with memory controller.
<Memory Controller Configuration>: Warns about issues with memory
controller and advises not to use it.
<Standalone Simulator>: Details for options with arguments updated.
* NEWS: Updated for 0.5.0rc2.
* peripheral/mc.c (mc_poc): Use constant MC_POC_VALID
(mc_index): Ensure value is valid.
* peripheral/mc-defines.h <MC_CE_VALID>: Defined.
* testsuite/test-code-or1k/configure: Regenerated.
* testsuite/test-code-or1k/configure.ac: Handle the case where
target_cpu is not set. Version changed to 0.5.0rc2.
* testsuite/test-code-or1k/support/spr-defs.h <SPR_VR_RES>:
Definition corrected. |
jeremybennett |
4978d 07h |
/openrisc/trunk/or1ksim/doc/ |
| 346 |
Changes to support Or1ksim 0.5.0rc1
Top level changes:
* config.h.in: Regenerated.
* debug.cfg, rsp.cfg: Deleted.
* doc/or1ksim.texi: Updated for new options and library interface.
* doc/or1ksim.info, doc/version.texi: Regenerated.
* Makefile.am: Added sim.cfg to EXTRA_DIST.
* NEWS: Updated for 0.5.0rc1.
* or1ksim.h <enum or1ksim_rc>: OR1KSIM_RC_OK explicitly zero.
* sim.cfg: Updated for consistency with the user guide.
* sim-config.c (init_defconfig): 50000 as default VAPI port.
(alloc_memory_block): Verbose message of amount allocated.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.
Changes in testsuite:
* libsim.tests/int-edge.exp <int-edge simple 1>: Increase time
between interrupts to 2ms.
<int-edge simple 2>: Increase time between interrupts to 2ms.
<int-edge duplicated 1>: Increase time between interrupts to 2ms.
<int-edge duplicated 2>: Increase time between interrupts to 2ms.
Changes in testsuite/test-code-or1k:
* mc-common/except-mc.S: Remove leading underscores from global
symbols.
* except/except.S: Remove leading underscores from global symbols.
* cache/cache-asm.S: Remove leading underscores from global symbols.
* cache/cache.c (jump_and_link): Remove leading underscore from
label.
(jump): Remove leading underscore from label.
(all): Remove leading underscore from global symbol references.
* testfloat/systfloat.S: Remove leading underscores from global
symbols.
* mmu/mmu.c (jump): Remove leading underscore from label.
* mmu/mmu-asm.S: Remove leading underscores from global symbols.
* except-test/except-test.c: Remove leading underscores from
global symbols.
* except-test/except-test-s.S: Remove leading underscores from
global symbols.
* uos/except-or32.S: Remove leading underscores from global
symbols.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1. |
jeremybennett |
5003d 09h |
/openrisc/trunk/or1ksim/doc/ |
| 240 |
or1ksim build fixups for Cygwin copilation |
julius |
5033d 12h |
/openrisc/trunk/or1ksim/doc/ |
