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[/] [openrisc/] [trunk/] [or1ksim/] [testsuite/] [test-code-or1k/] [except-test/] [except-test-s.S] - Rev 787

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787 Patch from R Diez to zero R0 on startup. ChangeLog from testsuite/test-code-or1k:

2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com>

Patch from R Diez <rdiezmail-openrisc@yahoo.de>

* cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S,
* except/except.S, ext/ext.S, flag/flag.S, fp/fp.S,
* inst-set-test/inst-set-test.S, int-test/int-test.S,
* mc-common/except-mc.S, uos/except-or32.S: Clear R0 on
start-up. There is no guarantee that R0 is hardwired to zero, and
indeed it is not when simulating the or1200 Verilog core.
* configure: Regenerated.
* configure.ac: Updated version.		 jeremybennett 4438d 12h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/except-test-s.S
458 or1ksim testsuite updates julius 4882d 16h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/except-test-s.S
346 Changes to support Or1ksim 0.5.0rc1

Top level changes:

* config.h.in: Regenerated.
* debug.cfg, rsp.cfg: Deleted.
* doc/or1ksim.texi: Updated for new options and library interface.
* doc/or1ksim.info, doc/version.texi: Regenerated.
* Makefile.am: Added sim.cfg to EXTRA_DIST.
* NEWS: Updated for 0.5.0rc1.
* or1ksim.h <enum or1ksim_rc>: OR1KSIM_RC_OK explicitly zero.
* sim.cfg: Updated for consistency with the user guide.
* sim-config.c (init_defconfig): 50000 as default VAPI port.
(alloc_memory_block): Verbose message of amount allocated.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.

Changes in testsuite:

* libsim.tests/int-edge.exp <int-edge simple 1>: Increase time
between interrupts to 2ms.
<int-edge simple 2>: Increase time between interrupts to 2ms.
<int-edge duplicated 1>: Increase time between interrupts to 2ms.
<int-edge duplicated 2>: Increase time between interrupts to 2ms.

Changes in testsuite/test-code-or1k:

* mc-common/except-mc.S: Remove leading underscores from global
symbols.
* except/except.S: Remove leading underscores from global symbols.
* cache/cache-asm.S: Remove leading underscores from global symbols.
* cache/cache.c (jump_and_link): Remove leading underscore from
label.
(jump): Remove leading underscore from label.
(all): Remove leading underscore from global symbol references.
* testfloat/systfloat.S: Remove leading underscores from global
symbols.
* mmu/mmu.c (jump): Remove leading underscore from label.
* mmu/mmu-asm.S: Remove leading underscores from global symbols.
* except-test/except-test.c: Remove leading underscores from
global symbols.
* except-test/except-test-s.S: Remove leading underscores from
global symbols.
* uos/except-or32.S: Remove leading underscores from global
symbols.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.		 jeremybennett 5001d 10h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/except-test-s.S
90 Reorganized to allow tests with both native code (for the library) and OpenRISC code (which requires the target tool chain). jeremybennett 5140d 05h /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/except-test-s.S

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