OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] - Rev 858

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
858 orpsoc/tests: Fix or1200-dsxinsn when caches are not present

This test would go into an endless loop when caches are not present.
stekern 4072d 06h /openrisc/trunk/orpsocv2/sw/tests/
807 ORPSoC: Commit for bug 85 - add DSX support to OR1200.

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85

Also added software tests, and added these tests to default regression test list
julius 4369d 20h /openrisc/trunk/orpsocv2/sw/tests/
805 ORPSoC: Fix for bug 90 - EPCR on range exception bug

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90
julius 4369d 20h /openrisc/trunk/orpsocv2/sw/tests/
803 ORPSoC: Fix for bug 91, l.sub not setting overflow flag correctly

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91
julius 4369d 21h /openrisc/trunk/orpsocv2/sw/tests/
801 ORPSoC: Fix bug 88

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88
julius 4375d 02h /openrisc/trunk/orpsocv2/sw/tests/
672 ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled

OR1200 RTL fix and software test added.
julius 4535d 21h /openrisc/trunk/orpsocv2/sw/tests/
671 ORPSoC: Fix for Bug 75 - or1200-except and or1200-ticksyscall regression tests failing due to change in memory model julius 4535d 21h /openrisc/trunk/orpsocv2/sw/tests/
655 ORPSoC: add CFI flash controller to ml501, sw driver, tests, app, documentation julius 4586d 23h /openrisc/trunk/orpsocv2/sw/tests/
619 ORPSoC OR1200 fix and regression test for bug 51.

signed-off Julius Baxter
reviewed by Stefan Kristiansson
julius 4667d 22h /openrisc/trunk/orpsocv2/sw/tests/
567 ORPSoC ethmac test and diagnosis software program updates. julius 4699d 12h /openrisc/trunk/orpsocv2/sw/tests/
535 ORPSoC - adding sw tests for l.rfe julius 4759d 01h /openrisc/trunk/orpsocv2/sw/tests/
530 ORPSoC update

Ethernet MAC Wishbone interface fixes

Beginnings of software update.

ML501 backend script fixes for new ISE
julius 4766d 10h /openrisc/trunk/orpsocv2/sw/tests/
506 ORPSoC or1200 interrupt and syscall generation test julius 4792d 04h /openrisc/trunk/orpsocv2/sw/tests/
504 ORPSoC ALU update with new comparison configuration option, software test for comparisons and register file comment cleanup julius 4809d 01h /openrisc/trunk/orpsocv2/sw/tests/
502 ORPSoC update - or1200, ethmac Xilinx fifos
or1200 in ORPSoC has carry bit, overflow bit, and range exception added and tested. New software tests in ORPSoC library. Ml501 build had ethmac fifos added, and or1200_defines updated to use these new or1200 features by default
julius 4812d 01h /openrisc/trunk/orpsocv2/sw/tests/
499 ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup julius 4813d 21h /openrisc/trunk/orpsocv2/sw/tests/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4816d 08h /openrisc/trunk/orpsocv2/sw/tests/
489 ORPSoC sw cleanup. Remove warnings. julius 4840d 07h /openrisc/trunk/orpsocv2/sw/tests/
488 ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. julius 4840d 08h /openrisc/trunk/orpsocv2/sw/tests/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4847d 10h /openrisc/trunk/orpsocv2/sw/tests/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.