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[/] [pairing/] [trunk/] - Rev 30

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Rev Log message Author Age Path
30 LGPL header homer.xing 4467d 18h /pairing/trunk/
29 default net type is wire homer.xing 4474d 14h /pairing/trunk/
28 Non-net port XXX cannot be of mode input, when using the "`default_nettype none" to turn off automatic inference of wires in the design. ha ha homer.xing 4474d 17h /pairing/trunk/
27 definition for undefined wire homer.xing 4474d 18h /pairing/trunk/
26 Detailed description for the ModelSim macro file and the main test bench file homer.xing 4480d 14h /pairing/trunk/
25 simulation scripts and readme-file explaining how to start the simulation homer.xing 4480d 14h /pairing/trunk/
24 LGPL claim in each source hdl file homer.xing 4488d 14h /pairing/trunk/
23 LGPL license text homer.xing 4488d 14h /pairing/trunk/
22 Change TAB to space homer.xing 4488d 16h /pairing/trunk/
21 Add detailed input data capture condition in the document homer.xing 4488d 16h /pairing/trunk/
20 Add a module and a testbench for Xilinx ISE post-route simulation homer.xing 4489d 18h /pairing/trunk/
19 Update synthesis result homer.xing 4490d 11h /pairing/trunk/
18 add synthesis result homer.xing 4490d 12h /pairing/trunk/
17 use logic for $f3m_mux6$ homer.xing 4490d 13h /pairing/trunk/
16 Add synthesis configuration files homer.xing 4490d 16h /pairing/trunk/
15 add document. ha ha ha homer.xing 4490d 17h /pairing/trunk/
14 Move constraint file homer.xing 4490d 18h /pairing/trunk/
13 Add document and synthesis directories homer.xing 4490d 18h /pairing/trunk/
12 Simplify the interface of the core. homer.xing 4490d 19h /pairing/trunk/
11 Cheers! as fast as a rocket homer.xing 4491d 14h /pairing/trunk/

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