OpenCores
URL https://opencores.org/ocsvn/pairing/pairing/trunk

Subversion Repositories pairing

[/] [pairing/] [trunk/] - Rev 33

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
33 new email & English name of the author homer.xing 4443d 05h /pairing/trunk/
32 changed surname: Xing -> Hsing. homer.xing 4443d 05h /pairing/trunk/
31 accurate source code copyright comment header homer.xing 4443d 05h /pairing/trunk/
30 LGPL header homer.xing 4453d 09h /pairing/trunk/
29 default net type is wire homer.xing 4460d 06h /pairing/trunk/
28 Non-net port XXX cannot be of mode input, when using the "`default_nettype none" to turn off automatic inference of wires in the design. ha ha homer.xing 4460d 09h /pairing/trunk/
27 definition for undefined wire homer.xing 4460d 09h /pairing/trunk/
26 Detailed description for the ModelSim macro file and the main test bench file homer.xing 4466d 05h /pairing/trunk/
25 simulation scripts and readme-file explaining how to start the simulation homer.xing 4466d 05h /pairing/trunk/
24 LGPL claim in each source hdl file homer.xing 4474d 05h /pairing/trunk/
23 LGPL license text homer.xing 4474d 06h /pairing/trunk/
22 Change TAB to space homer.xing 4474d 07h /pairing/trunk/
21 Add detailed input data capture condition in the document homer.xing 4474d 07h /pairing/trunk/
20 Add a module and a testbench for Xilinx ISE post-route simulation homer.xing 4475d 10h /pairing/trunk/
19 Update synthesis result homer.xing 4476d 03h /pairing/trunk/
18 add synthesis result homer.xing 4476d 03h /pairing/trunk/
17 use logic for $f3m_mux6$ homer.xing 4476d 05h /pairing/trunk/
16 Add synthesis configuration files homer.xing 4476d 08h /pairing/trunk/
15 add document. ha ha ha homer.xing 4476d 09h /pairing/trunk/
14 Move constraint file homer.xing 4476d 10h /pairing/trunk/
13 Add document and synthesis directories homer.xing 4476d 10h /pairing/trunk/
12 Simplify the interface of the core. homer.xing 4476d 10h /pairing/trunk/
11 Cheers! as fast as a rocket homer.xing 4477d 06h /pairing/trunk/
10 Ho ho, better circuit homer.xing 4478d 00h /pairing/trunk/
9 Add constrains file for ISE homer.xing 4479d 04h /pairing/trunk/
8 Finished Tate Pairing. Ha ha ha homer.xing 4479d 04h /pairing/trunk/
7 Finish inversion @ f33m homer.xing 4487d 09h /pairing/trunk/
6 add testbench for $f33m$. homer.xing 4488d 09h /pairing/trunk/
5 rename director : verilog/ -> rtl/ homer.xing 4488d 09h /pairing/trunk/
4 add testbench homer.xing 4489d 07h /pairing/trunk/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.