URL https://opencores.org/ocsvn/pairing/pairing/trunk

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[/] [pairing/] [trunk/] [rtl/] [f3m.v] - Rev 30

Rev	Log message	Author	Age	Path
30	LGPL header	homer.xing	4467d 16h	/pairing/trunk/rtl/f3m.v
28	Non-net port XXX cannot be of mode input, when using the "`default_nettype none" to turn off automatic inference of wires in the design. ha ha	homer.xing	4474d 16h	/pairing/trunk/rtl/f3m.v
24	LGPL claim in each source hdl file	homer.xing	4488d 12h	/pairing/trunk/rtl/f3m.v
22	Change TAB to space	homer.xing	4488d 14h	/pairing/trunk/rtl/f3m.v
17	use logic for $f3m_mux6$	homer.xing	4490d 11h	/pairing/trunk/rtl/f3m.v
11	Cheers! as fast as a rocket	homer.xing	4491d 13h	/pairing/trunk/rtl/f3m.v
8	Finished Tate Pairing. Ha ha ha	homer.xing	4493d 11h	/pairing/trunk/rtl/f3m.v
7	Finish inversion @ f33m	homer.xing	4501d 16h	/pairing/trunk/rtl/f3m.v
5	rename director : verilog/ -> rtl/	homer.xing	4502d 16h	/pairing/trunk/rtl/f3m.v
3	finish Duursma Lee algorithm. doing f33m module	homer.xing	4503d 14h	/pairing/trunk/verilog/f3m.v
2	upload code for Duursma-Lee algorithm. I am still developing them.	homer.xing	4504d 14h	/pairing/trunk/verilog/f3m.v