URL https://opencores.org/ocsvn/pairing/pairing/trunk

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[/] [pairing/] [trunk/] [rtl/] [inc.v] - Rev 29

Rev	Log message	Author	Age	Path
29	default net type is wire	homer.xing	4474d 18h	/pairing/trunk/rtl/inc.v
27	definition for undefined wire	homer.xing	4474d 21h	/pairing/trunk/rtl/inc.v
24	LGPL claim in each source hdl file	homer.xing	4488d 17h	/pairing/trunk/rtl/inc.v
5	rename director : verilog/ -> rtl/	homer.xing	4502d 21h	/pairing/trunk/rtl/inc.v
3	finish Duursma Lee algorithm. doing f33m module	homer.xing	4503d 19h	/pairing/trunk/verilog/inc.v
2	upload code for Duursma-Lee algorithm. I am still developing them.	homer.xing	4504d 19h	/pairing/trunk/verilog/inc.v