URL https://opencores.org/ocsvn/pdp1/pdp1/trunk

Subversion Repositories pdp1

[/] [pdp1/] [trunk/] - Rev 14

Rev	Log message	Author	Age	Path
14	Streaming data input in Rust oscilloscope. Next up: Non-blocking input.	yannv	2588d 12h	/pdp1/trunk/
13	Proof of concept Rust+Glium XY oscilloscope code. To do: add input capability and proper time keeping.	yannv	2589d 08h	/pdp1/trunk/
12	Proof of concept XY plotting in HTML canvas Performance on my workstation is just about fast enough. Work on a means of feeding points in.	yannv	2589d 13h	/pdp1/trunk/
11	Rough xy oscilloscope display program. Not actually usable, way too slow.	yannv	2591d 04h	/pdp1/trunk/
10	testtop: use a uart to send serial data	yannv	2591d 06h	/pdp1/trunk/
9	Avoid unsigned port for PC.	yannv	2591d 07h	/pdp1/trunk/
8	Avoid inout signal.	yannv	2591d 07h	/pdp1/trunk/
7	Typo fix.	yannv	2591d 07h	/pdp1/trunk/
6	Modified to use dual-port RAM for scanline buffers, instead of one RAM per scanline. Note that XST fails to create dual-port RAM if write data on one port is constant! Next step is to use generic_dpram from opencores common.	yannv	4819d 10h	/pdp1/trunk/
5	Add _i and _o suffixes to ports.	yannv	4819d 12h	/pdp1/trunk/
4	Filled in some comments in vector2scanline.v. My very first Verilog module, bear with me.	yannv	4832d 06h	/pdp1/trunk/
3	Unpacked source code for further development in svn.	yannv	4832d 07h	/pdp1/trunk/
2	Added Mercurial bundle of pre-subversion source code.	yannv	4832d 07h	/pdp1/trunk/
1	The project and the structure was created	root	4833d 08h	/pdp1/trunk/