URL https://opencores.org/ocsvn/pdp1/pdp1/trunk

Subversion Repositories pdp1

[/] [pdp1/] [trunk/] [rtl/] - Rev 17

Rev	Log message	Author	Age	Path
17	Very hacky code to read paper tape files. Isim reads integers as 32-bit signed little endian, so we split that into the constituent bytes. Simulation has now managed to use our preloaded readin program to read the RIM of same program, which contains another type of loader (with checksumming), which read the program in again. That's a lot of work for no real progress, but the computer loads code. To do: hardwired logic read in mode, tool to feed RIM files to hardware, possibly a way to load new tapes in simulation.	yannv	2575d 08h	/pdp1/trunk/rtl/
10	testtop: use a uart to send serial data	yannv	2578d 08h	/pdp1/trunk/rtl/
9	Avoid unsigned port for PC.	yannv	2578d 09h	/pdp1/trunk/rtl/
8	Avoid inout signal.	yannv	2578d 09h	/pdp1/trunk/rtl/
7	Typo fix.	yannv	2578d 09h	/pdp1/trunk/rtl/
6	Modified to use dual-port RAM for scanline buffers, instead of one RAM per scanline. Note that XST fails to create dual-port RAM if write data on one port is constant! Next step is to use generic_dpram from opencores common.	yannv	4806d 12h	/pdp1/trunk/rtl/
5	Add _i and _o suffixes to ports.	yannv	4806d 14h	/pdp1/trunk/rtl/
4	Filled in some comments in vector2scanline.v. My very first Verilog module, bear with me.	yannv	4819d 08h	/pdp1/trunk/rtl/
3	Unpacked source code for further development in svn.	yannv	4819d 09h	/pdp1/trunk/rtl/
2	Added Mercurial bundle of pre-subversion source code.	yannv	4819d 09h	/pdp1/trunk/rtl/