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[/] [pit/] [trunk/] - Rev 24

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Rev	Log message	Author	Age	Path
24	Added System Verilog Wishbone interface to module and testbench.	rehayes	4575d 04h	/pit/trunk/
23	Simple language upgrade, will make bigger changes to add more system verilog features later.	rehayes	4660d 15h	/pit/trunk/
22	Correct revision, compiles with VCS.	rehayes	4660d 15h	/pit/trunk/
21	Simple language upgrade	rehayes	4661d 08h	/pit/trunk/
20	minor update for timing constraint sugestions.	rehayes	5196d 10h	/pit/trunk/
19	Minor change to add parameter to pit instance	rehayes	5196d 10h	/pit/trunk/
18	Traded 16 data registers for 3 address registers when wait states are enabled.	rehayes	5196d 13h	/pit/trunk/
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5210d 09h	/pit/trunk/
16	Added master error counter variable, added simulation timout limit	rehayes	5321d 12h	/pit/trunk/
15	Fix blocking assigment	rehayes	5349d 13h	/pit/trunk/
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5418d 10h	/pit/trunk/
13	Update to rev 0.3, added SINGLE_CYCLE parameter	rehayes	5448d 14h	/pit/trunk/
12	Fixed for single cycle reads	rehayes	5449d 09h	/pit/trunk/
11	Changed read task to capture data at rising edge of clock	rehayes	5449d 09h	/pit/trunk/
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5450d 12h	/pit/trunk/
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5456d 06h	/pit/trunk/
8	Fix ack signal in testbench	rehayes	5456d 06h	/pit/trunk/
7	Reflection of minor corrections	rehayes	5460d 12h	/pit/trunk/
6	Reflection of minor corrections	rehayes	5460d 12h	/pit/trunk/
5		rehayes	5498d 08h	/pit/trunk/

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[/] [pit/] [trunk/] - Rev 24

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