URL https://opencores.org/ocsvn/reed_solomon_decoder/reed_solomon_decoder/trunk

Subversion Repositories reed_solomon_decoder

[/] [reed_solomon_decoder/] [trunk/] [simulation/] - Rev 4

Rev	Log message	Author	Age	Path
4	Added simulation & synthesis scripts.	vk.semiconductors	5137d 11h	/reed_solomon_decoder/trunk/simulation/
3	* Read_me.txt file is added, the file contains the description of the simulation files.	vk.semiconductors	5403d 16h	/reed_solomon_decoder/trunk/simulation/
2	Initial commit of Reed Solomon Decoder Verilog core (204,188,8) corrects up to 8 errors per block Pipelined and verfied on FPGA	aelmahmoudy	5416d 15h	/reed_solomon_decoder/trunk/simulation/