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Subversion Repositories rs232_interface

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Rev Log message Author Age Path
18 Added RX state verification for start bit process.
Added loop in the parallel interface of TB.		 akram.mashni 4330d 11h /
17 First commit of uart test bench.
WARNING: Not yet finished! Commited for back up.		 akram.mashni 4762d 19h /
16 Project's block diagram.
It will be use in the datasheet.
(Compression level 5 when export from .odg file).		 akram.mashni 4864d 04h /
15 Removed uncompressed image with big size. akram.mashni 4864d 04h /
14 Block diagram image of 2011-01-16 version.
It will be use in the datasheet.
(Compression level 5 when export from .odg file).		 akram.mashni 4864d 05h /
13 Initial commit of documentation.
Created block diagram (OpenOffice Draw format).		 akram.mashni 4864d 05h /
12 Updated news of uart.vhd commit. akram.mashni 4865d 08h /
11 Moved debouncer to a new process.
Fixed rx_clk_en generation.
Fixed start of reception condition on rx FSM.		 akram.mashni 4865d 08h /
10 Implemented asynchronous mode and RX clock regeneration.
NOT TESTED !!!		 akram.mashni 4873d 02h /
9 Updated change log. akram.mashni 4910d 17h /
8 Added Recommended Tools akram.mashni 4910d 17h /
7 Implemented PARITY (not tested!). akram.mashni 4912d 03h /
6 Fixed/improved header.
Changed SPACEs to TABs.		 akram.mashni 4913d 09h /
5 Added comments to port map. akram.mashni 4920d 13h /
4 Added "Change Log".
Added "About"		 akram.mashni 4920d 14h /
3 Added main file.
Fisrt commit.
Tested in the following conditions:
- Baud rate: 9600 bps.
- Implementation: Xilinx Spartan3e500 (Nexys2 Kit - Digilent)
- Main clock 50 MHz		 akram.mashni 4920d 14h /
2 Initial Commit luciorp 4977d 03h /
1 The project and the structure was created root 5005d 00h /

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