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Subversion Repositories sdhc-sc-core

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Rev Log message Author Age Path
188 Declared all targets phony to force building. rkastl 4880d 15h /
187 Unit makefiles modified to reflect new location of Makefile.rules. rkastl 4880d 15h /
186 Makefile adapted to new paths. rkastl 4880d 15h /
185 Restructuring as source repository: Moved sources out of src subdirectory. rkastl 4880d 15h /
184 Removed WbSlave shell (refs #69)
Moved verification sources to grpSdVerification (fixes #70)		 rkastl 4883d 09h /
183 Removed unneeded wrapper (refs #69)
Sector count increased in TestWbMaster (refs #78)		 rkastl 4883d 09h /
182 Fixes #60.

Synchronization logic moved to its own unit.		 rkastl 4883d 09h /
181 Refs #60.

Fix synthesis with seperate WbClkDomain.		 rkastl 4883d 09h /
180 Moved WbClkDomain to its own unit.
Refs #60.		 rkastl 4883d 09h /
179 Fixing build:
Added library generation to Makefile.		 rkastl 4883d 09h /
178 Fixed regression:
Testbenches did not support synchronous reset.		 rkastl 4883d 09h /
177 Split SdTop into SdClkDomain and SdTop. Refs #60. rkastl 4883d 09h /
176 Thesis:
Conclusion

Fixes #53,#61.		 rkastl 4883d 09h /
175 Thesis:

Fixes #45.		 rkastl 4883d 09h /
174 Thesis:
System integration

Fixes #51.		 rkastl 4883d 09h /
173 Thesis:
Started with SdController description.

Refs #38.		 rkastl 4883d 09h /
172 Thesis:
wbclockdomain: refactored and finished.

Fixes #39.		 rkastl 4883d 09h /
171 Worked on wishbone part of thesis.

Refs #37.
Refs #39.		 rkastl 4883d 09h /
170 License rewritten to BSD rkastl 4883d 09h /
169 +sdc file for timing analysis rkastl 4883d 09h /
168 TbdSd synthesis script reaches timing constraints. rkastl 4883d 09h /
167 Read+Modify+Write works on HW

+ Fixed CRC status token (not mentioned in simplified spec)
+ Improved TestWbMaster to RMW		 rkastl 4883d 09h /
166 tbTbdSd: fixed rkastl 4883d 09h /
165 Only use synchronous high active reset in SDHC-SC-Core. rkastl 4883d 09h /
164 Headers updated (LGPL, consistent format) rkastl 4883d 09h /
163 Header-Skript supports writing to file and infile replacement. rkastl 4883d 09h /
162 Script for generating headers created. rkastl 4883d 09h /
161 Verification:
CardModel: Check CRC on received data		 rkastl 4883d 09h /
160 Verification:
Full random read and write single blocks sequence works with
checks.
Checking the CRC in the card model is missing.
Writing at addresses above the card size is missing.
Erasing is missing.		 rkastl 4883d 09h /
159 Verification:
Further work: Checking RAM Actions and reading data is still
missing		 rkastl 4883d 09h /

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