URL https://opencores.org/ocsvn/sdram_controller/sdram_controller/trunk

Subversion Repositories sdram_controller

[/] [sdram_controller/] - Rev 12

Rev	Log message	Author	Age	Path
12	1. rolled write recover clocks back to previous value and edited comments 2. increased 200us wait time to 300us in the init module	lynn0p	5353d 01h	/sdram_controller/
11	consolidated capture into one process and added comments	lynn0p	5353d 20h	/sdram_controller/
10	Fixes to more glitches uncovered during testing with my T80 SoC. Some ops were getting dropped on the floor when the controller needed to do an auto refresh.	lynn0p	5354d 01h	/sdram_controller/
9	Got rid of some redundant busy_n <= '0' statements	lynn0p	5355d 13h	/sdram_controller/
8	Changes made to integrate and test with my homebrew SoC design. 1. One DCM has been removed. Now requires a 100mhz clock fed in. Only consumes one DCM, if you can find a 100mhz clock somewhere. 2. Small timing modifications to fix memory glitches between controller and the t80 soft cpu I'm using.	lynn0p	5355d 13h	/sdram_controller/
7	Reformatted the comments so they fit in 80 columns	lynn0p	5363d 18h	/sdram_controller/
6	changes to reduce synthesizer warnings, removed unused signals, etc.	lynn0p	5363d 22h	/sdram_controller/
5	added header file for ddr.v	lynn0p	5364d 18h	/sdram_controller/
4	added testbench files to trunk	lynn0p	5364d 18h	/sdram_controller/
3	adding LGPLv3 license file	lynn0p	5364d 19h	/sdram_controller/
2	initial checkin	lynn0p	5364d 19h	/sdram_controller/
1	The project was created and the structure was created	root	5364d 22h	/sdram_controller/