URL https://opencores.org/ocsvn/sdram_controller/sdram_controller/trunk

Subversion Repositories sdram_controller

[/] [sdram_controller/] [trunk/] [scratch.vhd] - Rev 22

Rev	Log message	Author	Age	Path
22	Testbench was "broken" when I fixed controller for my SoC. This "fixes" the testbench so it works again, so that the testbench and my SoC both work.	lynn0p	5327d 14h	/sdram_controller/trunk/scratch.vhd
21	1. Updated testbench to reflect lack of en signal 2. Deleted tarball and replaced it with a project file and user constraints file	lynn0p	5327d 15h	/sdram_controller/trunk/scratch.vhd
14	Changed the clock period in the DCM generic to match 50mhz	lynn0p	5333d 16h	/sdram_controller/trunk/scratch.vhd
13	Updated the top level testbench to reflect the fact that you need an external DCM to run the controller with now.	lynn0p	5333d 17h	/sdram_controller/trunk/scratch.vhd
6	changes to reduce synthesizer warnings, removed unused signals, etc.	lynn0p	5353d 18h	/sdram_controller/trunk/scratch.vhd
4	added testbench files to trunk	lynn0p	5354d 13h	/sdram_controller/trunk/scratch.vhd