URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] - Rev 135

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
135	resynced with socgen, Release V1.0.0 changed tool lic to apache 2.0	jt_eaton	2754d 04h	/socgen/
134	Resynced database socgen now supports elaboration Bad news is that it is now alot slower.	jt_eaton	3264d 06h	/socgen/
133	Added Desing databases and foundation for elaborations tools	jt_eaton	3307d 07h	/socgen/
132	fixed permissions on tools/bin	jt_eaton	3339d 03h	/socgen/
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3339d 04h	/socgen/
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3442d 21h	/socgen/
129	removed unneeded 6502 files	jt_eaton	3898d 03h	/socgen/
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3898d 03h	/socgen/
127	final cleanup before DAC	jt_eaton	4012d 23h	/socgen/
126	added mor1kx cleanup	jt_eaton	4066d 04h	/socgen/
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4110d 22h	/socgen/
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4164d 01h	/socgen/
123	added support for ubuntu 12.10	jt_eaton	4178d 17h	/socgen/
122	Moved Nexys2 from opencores.org to digilentinc.com Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components	jt_eaton	4186d 20h	/socgen/
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4207d 02h	/socgen/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4225d 02h	/socgen/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4259d 21h	/socgen/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4295d 06h	/socgen/
117	added yellow pages tools	jt_eaton	4323d 01h	/socgen/
116	added build_header now use build_register for all spr components resynced or1200 code back to use orbuild toolchain	jt_eaton	4357d 22h	/socgen/
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4402d 02h	/socgen/
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4414d 02h	/socgen/
113	started refactoring or1200	jt_eaton	4419d 19h	/socgen/
112	added more test sims removed unneeded files	jt_eaton	4429d 07h	/socgen/
111	split or1200 out into seperate test suite	jt_eaton	4431d 02h	/socgen/
110	split out more ip-xact components added sw sources	jt_eaton	4442d 23h	/socgen/
109	removed unused file	jt_eaton	4445d 23h	/socgen/
108	removed unneeded files	jt_eaton	4447d 05h	/socgen/
107	added designCfg files to all modules	jt_eaton	4447d 08h	/socgen/
106	checked in orp_soc project step 2	jt_eaton	4453d 01h	/socgen/

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] - Rev 135

Filtering Options