URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Makefile] - Rev 135

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Rev	Log message	Author	Age	Path
135	resynced with socgen, Release V1.0.0 changed tool lic to apache 2.0	jt_eaton	2754d 01h	/socgen/trunk/Makefile
134	Resynced database socgen now supports elaboration Bad news is that it is now alot slower.	jt_eaton	3264d 03h	/socgen/trunk/Makefile
133	Added Desing databases and foundation for elaborations tools	jt_eaton	3307d 04h	/socgen/trunk/Makefile
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3339d 01h	/socgen/trunk/Makefile
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3442d 18h	/socgen/trunk/Makefile
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3898d 00h	/socgen/trunk/Makefile
127	final cleanup before DAC	jt_eaton	4012d 21h	/socgen/trunk/Makefile
126	added mor1kx cleanup	jt_eaton	4066d 01h	/socgen/trunk/Makefile
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4110d 19h	/socgen/trunk/Makefile
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4207d 00h	/socgen/trunk/Makefile
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4259d 18h	/socgen/trunk/Makefile
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4295d 03h	/socgen/trunk/Makefile
117	added yellow pages tools	jt_eaton	4322d 22h	/socgen/trunk/Makefile
113	started refactoring or1200	jt_eaton	4419d 16h	/socgen/trunk/Makefile
112	added more test sims removed unneeded files	jt_eaton	4429d 05h	/socgen/trunk/Makefile
106	checked in orp_soc project step 2	jt_eaton	4452d 22h	/socgen/trunk/Makefile
103	added user guide resynced to local repository	jt_eaton	4477d 20h	/socgen/trunk/Makefile
102	all ip-xact files now readable by kactus2	jt_eaton	4539d 15h	/socgen/trunk/Makefile
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4540d 17h	/socgen/trunk/Makefile
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4553d 01h	/socgen/trunk/Makefile

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Makefile] - Rev 135

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